Abstract: An electronic device includes a multilevel metallization structure, a semiconductor die, and a package structure. The multilevel metallization structure has multiple levels of conductive metal traces and vias and polyimide insulator material, including a first level along a first side and a final level along a second side. The first level includes conductive metal leads with exposed surfaces along the first side, and the final level includes conductive metal pads with exposed surfaces along the second side. The semiconductor die is flip chip attached to the first side of the multilevel metallization structure with conductive features connected to respective conductive metal pads of the final level of the multilevel metallization structure, and the package structure encloses the semiconductor die and portions of the first side of the multilevel metallization structure.

Abstract: An electronic device includes a metal heat slug, a semiconductor die, and a package structure. The metal heat slug has a first portion, a second portion, and a third portion, the second portion is spaced apart from the first portion, and the third portion connects the first and second portions. The semiconductor die is attached to the third portion of the metal heat slug to measure a current of the third portion of the metal heat slug, and the package structure encloses the semiconductor die and the third portion of the metal heat slug and exposes sides of the first and second portions of the metal heat slug.

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

Abstract: In some examples, a package comprises a platform and at least one pedestal positioned along at least a portion of a perimeter of the platform. The platform and the at least one pedestal form a cavity. The package also comprises a die positioned in the cavity and on the platform, with the die having an active circuit facing away from the platform. The package also comprises a conductive layer coupled to the die and to a conductive terminal. The conductive terminal is positioned above the at least one pedestal, and the die and the conductive terminal are positioned in different horizontal planes.

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

Abstract: A semiconductor device (100) comprises a semiconductor chip (310) attached to the pad (302) of a planar leadframe and connected by bonding wires (411) to two leads (403) of the leadframe. The device further includes a plastic body (130) encapsulating chip and wires, the body shaped as a pentahedron with two sides (101, 102) touching at right angle, opposite body ends formed by parallel planes configured as right-angle triangles. The pad (302) and the two leads (303) are exposed from the plastic surface at one body end in order to be operable as solderable device pins positioned in the corners of the triangle.

Abstract: A packaged sensor MEMS (100) has a semiconductor chip (101) with a protected cavity (102) including a sensor (105), the cavity surrounded by solder bumps (130) attached to the chip terminals; further a leadframe with elongated and radially positioned leads (131), the central lead ends (131a) attached to the bumps. Insulating material (120) encapsulates chip and central lead ends, leaving the chip surface (101a) opposite the cavity and the peripheral lead ends (131b) un-encapsulated. The un-encapsulated peripheral lead ends are bent into cantilevers for attachment to a horizontal substrate (160), the cantilevers having a geometry to accommodate, under a force lying in the plane of the substrate, elastic bending and stretching beyond the limit of simple elongation based upon inherent material characteristics, especially when supported by lead portions with curved, toroidal, or multiple-bendings geometries.

Abstract: A packaged sensor MEMS (100) has a semiconductor chip (101) with a protected cavity (102) including a sensor (105), the cavity surrounded by solder bumps (130) attached to the chip terminals; further a leadframe with elongated and radially positioned leads (131), the central lead ends (131a) attached to the bumps. Insulating material (120) encapsulates chip and central lead ends, leaving the chip surface (101a) opposite the cavity and the peripheral lead ends (131b) un-encapsulated. The un-encapsulated peripheral lead ends are bent into cantilevers for attachment to a horizontal substrate (160), the cantilevers having a geometry to accommodate, under a force lying in the plane of the substrate, elastic bending and stretching beyond the limit of simple elongation based upon inherent material characteristics, especially when supported by lead portions with curved, toroidal, or multiple-bendings geometries.

Abstract: A thin-contour semiconductor device with a solenoid and iron core integrated into the device package. The solenoid windings are constructed by a stripe-shaped layer portion, deposited on the chip surface, and an arced wire portion welded to the layer portion by low-cost standard wire bonding technique. The stripes are arrayed parallel to each other, spaced apart respective insulating gaps. The arced wires span from one stripe to the adjacent next stripe by bridging the gap and keeping the clock direction constant. The arced solenoid windings are then integrated into the encapsulating device package. The ferromagnetic core may be shaped as a ring to allow the formation of a strong and nearly homogeneous magnetic field inside the solenoid, providing reliable energy storage for power supply circuits.

Abstract: Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.