Patents by Inventor Sreeram Chandrasekar

Sreeram Chandrasekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110271241
    Abstract: A method includes jointly implementing a number of Intellectual Property (IP) sub-systems in a virtual design associated with one or more System-on-a-Chip(s) (SoC(s)) utilizing a design platform. Each sub-system of the number of IP sub-systems is associated with an IP configured to be a deliverable to the one or more SoC(s). The method also includes maintaining each sub-system of the number of IP sub-systems as an independent entity in the virtual design through an appropriate handling of a design closure and a timing closure. IPs associated with two or more IP sub-systems of the virtual design are related or unrelated to one another.
    Type: Application
    Filed: April 25, 2011
    Publication date: November 3, 2011
    Inventors: Hari Krishnamoorthy, Sreeram Chandrasekar
  • Patent number: 7284212
    Abstract: Reducing the number of computations required to pre-characterize cells in a cell-library. In an embodiment, a worst case vector which propagates most noise on an arc (combination of input pin and output pin) of a cell is determined, and NP characteristics and NIC are generated only for the worst case vector. Noise analysis is then performed using such curves generated from the worst case vector. Since curves corresponding to only the worst case vector may need to be generated, the computational requirements may be reduced. The search ranges in determining the immunity transition points forming the NIC may be reduced, according to some aspects of the present invention. The data corresponding to NIC may be used to generate NP curves, and vice versa to reduce computational requirements further.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: October 16, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gaurav Kumar Varshney, Sreeram Chandrasekar
  • Publication number: 20060015831
    Abstract: Reducing the number of computations required to pre-characterize cells in a cell-library. In an embodiment, a worst case vector which propagates most noise on an arc (combination of input pin and output pin) of a cell is determined, and NP characteristics and NIC are generated only for the worst case vector. Noise analysis is then performed using such curves generated from the worst case vector. Since curves corresponding to only the worst case vector may need to be generated, the computational requirements may be reduced. The search ranges in determining the immunity transition points forming the NIC may be reduced, according to some aspects of the present invention. The data corresponding to NIC may be used to generate NP curves, and vice versa to reduce computational requirements further.
    Type: Application
    Filed: July 16, 2004
    Publication date: January 19, 2006
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gaurav VARSHNEY, Sreeram CHANDRASEKAR