Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

Abstract: In a segmented data path, a source is able to “discover” whether any tunable repeater nodes are present. When one or more tunable repeaters are discovered, the source may adjust its link initialization sequence accordingly to train each “hop” individually and thereafter individually configure each intermediary repeater.

Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

Abstract: Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

Abstract: Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

Abstract: A display system includes a host device that provides source data to a display. The source data includes one or more data-centric blocks free from a fixed-frame size imposition, fixed-frame rate imposition, or both from the display. Further, the source data includes presentation data. The display system includes a display that receives the source data, decodes the source data to discern a presentation time, a presentation positioning, or both for the presentation data. Further, the display presents the presentation data according to the presentation time, the presentation positioning, or both.

Abstract: An electronic device selectively couples a head with links in a graphics processing unit to a currently selected display port in a pair of display ports. During operation, control logic in the electronic device monitors a pair of configuration signals from the pair of display ports, where the pair of configuration signals correspond to physical connections to the pair of display ports. Then, the control logic determines a selection control signal based on the monitored pair of configuration signals, a policy setting and a default display port, where the selection control signal specifies the currently selected display port. Moreover, the control logic provides the selection control signal to a multiplexer in the electronic device. Next, the multiplexer selectively couples the head with the links in the graphics processing unit to the currently selected display port based on the selection control signal.

Abstract: An electronic device selectively couples a head with links in a graphics processing unit to a currently selected display port in a pair of display ports. During operation, control logic in the electronic device monitors a pair of configuration signals from the pair of display ports, where the pair of configuration signals correspond to physical connections to the pair of display ports. Then, the control logic determines a selection control signal based on the monitored pair of configuration signals, a policy setting and a default display port, where the selection control signal specifies the currently selected display port. Moreover, the control logic provides the selection control signal to a multiplexer in the electronic device. Next, the multiplexer selectively couples the head with the links in the graphics processing unit to the currently selected display port based on the selection control signal.

Abstract: In a segmented data path, a source is able to “discover” whether any tunable repeater nodes are present. When one or more tunable repeaters are discovered, the source may adjust its link initialization sequence accordingly to train each “hop” individually and thereafter individually configure each intermediary repeater.

Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

Abstract: Methods and apparatus for packing and transporting data within an electronic device. In one embodiment, a consumer electronics device having one or more sensors (e.g., camera sensors) uses modified DisplayPort micro-packets for transmission of RAW format data over one or more lanes of a DisplayPort Main Steam. The RAW data is transported over the one or more lanes by mapping symbol sequences generated from the RAW data based on Y-only data mappings schemes of DisplayPort. A mapping scheme is in one variant selected based on the bits length (e.g., bits per pixel) of the RAW data, in addition to the number of lanes used to transport over the Main Stream. In order for the sink correctly unpack received the micro-packets, the transmitting source transmits Main Stream Attribute (MSA) data packets configured to indicate at least the mapping scheme used.

Abstract: An electronic device selectively couples a head with links in a graphics processing unit to a currently selected display port in a pair of display ports. During operation, control logic in the electronic device monitors a pair of configuration signals from the pair of display ports, where the pair of configuration signals correspond to physical connections to the pair of display ports. Then, the control logic determines a selection control signal based on the monitored pair of configuration signals, a policy setting and a default display port, where the selection control signal specifies the currently selected display port. Moreover, the control logic provides the selection control signal to a multiplexer in the electronic device. Next, the multiplexer selectively couples the head with the links in the graphics processing unit to the currently selected display port based on the selection control signal.

Abstract: Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

Abstract: An electronic device selectively couples a head with links in a graphics processing unit to a currently selected display port in a pair of display ports. During operation, control logic in the electronic device monitors a pair of configuration signals from the pair of display ports, where the pair of configuration signals correspond to physical connections to the pair of display ports. Then, the control logic determines a selection control signal based on the monitored pair of configuration signals, a policy setting and a default display port, where the selection control signal specifies the currently selected display port. Moreover, the control logic provides the selection control signal to a multiplexer in the electronic device. Next, the multiplexer selectively couples the head with the links in the graphics processing unit to the currently selected display port based on the selection control signal.