Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

Abstract: Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.

Abstract: Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.

Abstract: During a pop phase of hierarchical repartitioning of an IC design, all cells within a current hierarchy may be identified, the list of cells may be ungrouped to dissolve the current hierarchy, one or more specified cells may be removed from the list of cells, where the specified one or more cells are to be moved to a different hierarchy, and the new list of cells without the specified one or more cells may be re-grouped, to re-form the previously dissolved hierarchy. During a push phase of the hierarchical repartitioning, all cells within the next lower-level hierarchy may be identified, the identified list of cells may be ungrouped to dissolve that hierarchy, the specified one or more cells may be added to the identified list of cells, and the new list of cells that includes the specified one or more cells may be grouped to reform the previously dissolved hierarchy.

Abstract: During a pop phase of hierarchical repartitioning of an IC design, all cells within a current hierarchy may be identified, the list of cells may be ungrouped to dissolve the current hierarchy, one or more specified cells may be removed from the list of cells, where the specified one or more cells are to be moved to a different hierarchy, and the new list of cells without the specified one or more cells may be re-grouped, to re-form the previously dissolved hierarchy. During a push phase of the hierarchical repartitioning, all cells within the next lower-level hierarchy may be identified, the identified list of cells may be ungrouped to dissolve that hierarchy, the specified one or more cells may be added to the identified list of cells, and the new list of cells that includes the specified one or more cells may be grouped to reform the previously dissolved hierarchy.

Abstract: Direct memory access control may utilize a direct memory access register adapted to hold a descriptor.

Abstract: Direct memory access control may utilize a direct memory access register adapted to hold a descriptor.