Patents by Inventor Sri Chaitra Chavali

Sri Chaitra Chavali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200412041
    Abstract: A wide bandwidth signal connector plug, comprising a plurality of signal pins having a first anchor portion and a first mating portion, and a plurality of ground pins having a second anchor portion and a second mating portion. The plurality of ground pins is adjacent to the plurality of signal pins. The plurality of signal pins has a first thickness and the plurality of ground pins has a second thickness that is greater than the first thickness. The first anchor portion has a first width and the second anchor portion has a second width that is greater than the first width.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Zhenguo Jiang, Omkar Karhade, Sri Chaitra Chavali, William Lambert, Zhichao Zhang, Mitul Modi
  • Publication number: 20200051899
    Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 13, 2020
    Inventors: Debendra MALLIK, Sanka GANESAN, Pilin LIU, Shawna LIFF, Sri Chaitra CHAVALI, Sandeep GAAN, Jimin YAO, Aastha UPPAL
  • Patent number: 10553453
    Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Chavali, Siddharth K. Alur, Amanda E. Schuckman, Amruthavalli Palla Alur, Islam A. Salama, Yikang Deng, Kristof Darmawikarta
  • Publication number: 20190393606
    Abstract: Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Sri Chaitra CHAVALI, Siddharth ALUR, Sheng LI
  • Publication number: 20190311916
    Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimageable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.
    Type: Application
    Filed: July 14, 2016
    Publication date: October 10, 2019
    Inventors: Sri Chaitra CHAVALI, Siddharth K. ALUR, Amanda E. SCHUCKMAN, Amruthavalli Palla ALUR, Islam A. SALAMA, Yikang DENG, Kristof DARMAWIKARTA
  • Publication number: 20170174894
    Abstract: This document discusses, among other things, a stress-tolerant composite microelectronic material comprising a composite nanofiller including a nanofiller core material having a modulus greater than a core material composed of silicon dioxide (SiO2) alone, and an outer layer of oxidized nanofiller core material surrounding the nanofiller core material.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Sri Chaitra Chavali, Siddharth Alur, Amanda E. Schuckman