Patents by Inventor Sri Ganesh A. Tharumalingam
Sri Ganesh A. Tharumalingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240080977Abstract: According to an example, a structure is generally described. The structure may include an inductor core having a plurality of surfaces; and at least one conductor integrated with at least one surface of the plurality of surfaces of the inductor core.Type: ApplicationFiled: May 8, 2023Publication date: March 7, 2024Applicant: Renesas Electronics America Inc.Inventors: Zhizheng LIU, Haiyu ZHANG, Sri Ganesh A THARUMALINGAM, Mark Alan KWOKA, Yonggoo EOM
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Patent number: 11894352Abstract: A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.Type: GrantFiled: May 18, 2021Date of Patent: February 6, 2024Assignee: Renesas Electronics America Inc.Inventors: Sri Ganesh A Tharumalingam, Mark Kwoka, Viresh Piyush Patel, Peter Zhizheng Liu, Jeff Strang
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Publication number: 20220375909Abstract: A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Applicant: Renesas Electronics America Inc.Inventors: Sri Ganesh A Tharumalingam, Mark Kwoka, Viresh Piyush Patel, Peter Zhizheng Liu, Jeff Strang
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Patent number: 9721837Abstract: A method for wafer level fabricating a plurality of optoelectronic devices, starting with a wafer that includes a plurality of light detector sensor regions, includes attaching each of a plurality of light source dies to one of a plurality of bond pads on a top surface of the wafer that includes the plurality of light detector sensor regions. The method also includes attaching, to the wafer, a preformed opaque structure made off-wafer from an opaque material, wherein the preformed opaque structure includes opaque vertical optical barriers. Additionally, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is diced to separate the wafer into a plurality of optoelectronic devices, each of which includes at least one of the light detector sensor regions, at least one of the light source dies and at least two of the solder balls or other electrical connectors.Type: GrantFiled: June 24, 2015Date of Patent: August 1, 2017Assignee: INTERSIL AMERICAS LLCInventor: Sri Ganesh A Tharumalingam
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Patent number: 9570649Abstract: Optoelectronic devices (e.g., optical proximity sensors), methods for fabricating optoelectronic devices, and systems including optoelectronic devices, are described herein. An optoelectronic device includes a light detector die that includes a light detector sensor area. A light source die is attached to a portion of the light detector die that does not include the light detector sensor area. An opaque barrier is formed between the light detector sensor area and the light source die, and a light transmissive material encapsulates the light detector sensor area and the light source die. Rather than requiring a separate base substrate (e.g., a PCB substrate) to which are connected a light source die and a light detector die, the light source die is connected to the light detector die, such that the light detector die acts as the base for the finished optoelectronic device. This provides for cost reductions and reduces the total package footprint.Type: GrantFiled: March 27, 2015Date of Patent: February 14, 2017Assignee: INTERSIL AMERICAS LLCInventors: Sri Ganesh A. Tharumalingam, Seck Jiong Wong
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Patent number: 9570648Abstract: Optoelectronic devices (e.g., optical proximity sensors), methods for fabricating optoelectronic devices, and systems including optoelectronic devices, are described herein. An optoelectronic device includes a light detector die that includes a light detector sensor area. A light source die is attached to a portion of the light detector die that does not include the light detector sensor area. An opaque barrier is formed between the light detector sensor area and the light source die, and a light transmissive material encapsulates the light detector sensor area and the light source die. Rather than requiring a separate base substrate (e.g., a PCB substrate) to which are connected a light source die and a light detector die, the light source die is connected to the light detector die, such that the light detector die acts as the base for the finished optoelectronic device. This provides for cost reductions and reduces the total package footprint.Type: GrantFiled: February 7, 2013Date of Patent: February 14, 2017Assignee: INTERSIL AMERICAS LLCInventors: Sri Ganesh A. Tharumalingam, Seck Jiong Wong
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Publication number: 20160306072Abstract: An optical proximity sensor comprises a light detector die including a light detector sensor area and at least one bond pad on a portion of the light detector die not including the light detector sensor area. A light source die, including anode and cathode terminals, is attached to a portion of the light detector die not including the light detector sensor area, such that at least one of the terminals of the light source die, on a bottom of the light source die, is attached to at least one of the bond pads on the light detector die. An opaque barrier, formed off-wafer relative to a wafer including the light detector die, is attached to and extends upward from a top surface of the light detector die between the light detector sensor area and the light source die. Electrical connectors are on the bottom of the light detector die.Type: ApplicationFiled: February 29, 2016Publication date: October 20, 2016Applicant: Intersil Americas LLCInventor: Sri Ganesh A Tharumalingam
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Publication number: 20160307957Abstract: A method for wafer level fabricating a plurality of optoelectronic devices, starting with a wafer that includes a plurality of light detector sensor regions, includes attaching each of a plurality of light source dies to one of a plurality of bond pads on a top surface of the wafer that includes the plurality of light detector sensor regions. The method also includes attaching, to the wafer, a preformed opaque structure made off-wafer from an opaque material, wherein the preformed opaque structure includes opaque vertical optical barriers. Additionally, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is diced to separate the wafer into a plurality of optoelectronic devices, each of which includes at least one of the light detector sensor regions, at least one of the light source dies and at least two of the solder balls or other electrical connectors.Type: ApplicationFiled: June 24, 2015Publication date: October 20, 2016Applicant: INTERSIL AMERICAS LLCInventor: Sri Ganesh A Tharumalingam
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Patent number: 9305967Abstract: Described herein are methods for fabricating a plurality of optoelectronic devices, and the optoelectronic devices resulting from such methods. One such method includes performing through silicon via (TSV) processing on a wafer, which includes a plurality of light detector sensor regions, to thereby form a plurality of vias, and then tenting and plating the vias and performing wafer back metallization. Thereafter, plurality of light source dies are attached to a top surface of the wafer, and a light transmissive material is then molded to encapsulate the light detector sensor regions and the light sensor dies therein. Additionally, opaque barriers including opaque optical crosstalk barriers are fabricated. Further, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is eventually diced to separate the wafer into a plurality of optoelectronic devices.Type: GrantFiled: June 24, 2015Date of Patent: April 5, 2016Assignee: INTERSIL AMERICAS LLCInventor: Sri Ganesh A Tharumalingam
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Publication number: 20150207016Abstract: Optoelectronic devices (e.g., optical proximity sensors), methods for fabricating optoelectronic devices, and systems including optoelectronic devices, are described herein. An optoelectronic device includes a light detector die that includes a light detector sensor area. A light source die is attached to a portion of the light detector die that does not include the light detector sensor area. An opaque barrier is formed between the light detector sensor area and the light source die, and a light transmissive material encapsulates the light detector sensor area and the light source die. Rather than requiring a separate base substrate (e.g., a PCB substrate) to which are connected a light source die and a light detector die, the light source die is connected to the light detector die, such that the light detector die acts as the base for the finished optoelectronic device. This provides for cost reductions and reduces the total package footprint.Type: ApplicationFiled: March 27, 2015Publication date: July 23, 2015Inventors: Sri Ganesh A. Tharumalingam, Seck Jiong Wong
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Publication number: 20130334445Abstract: Optoelectronic devices (e.g., optical proximity sensors), methods for fabricating optoelectronic devices, and systems including optoelectronic devices, are described herein. An optoelectronic device includes a light detector die that includes a light detector sensor area. A light source die is attached to a portion of the light detector die that does not include the light detector sensor area. An opaque barrier is formed between the light detector sensor area and the light source die, and a light transmissive material encapsulates the light detector sensor area and the light source die. Rather than requiring a separate base substrate (e.g., a PCB substrate) to which are connected a light source die and a light detector die, the light source die is connected to the light detector die, such that the light detector die acts as the base for the finished optoelectronic device. This provides for cost reductions and reduces the total package footprint.Type: ApplicationFiled: February 7, 2013Publication date: December 19, 2013Applicant: INTERSIL AMERICAS LLCInventors: Sri Ganesh A. Tharumalingam, Seck Jiong Wong
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Publication number: 20060125115Abstract: A manufacturing technique that involves embedding one or more semiconductor die into a support substrate and forming conductive traces that lead from die contact pads to redistributed contact pads on the support substrate. Active surfaces of the dice and a working surface of the support substrate are substantially coplanar and the conductive traces are formed on the coplanar surfaces. The redistributed contact pads are sufficiently spaced apart from each other so that conductive balls can be formed thereon. Individual semiconductor device packages are singulated from the support substrate.Type: ApplicationFiled: February 8, 2006Publication date: June 15, 2006Inventors: Lee Chee, Sri Ganesh A. Tharumalingam