Abstract: Apparatus and methods disclosed herein implement steady-state and fast transient electronic current limiting through power transistors, including power transistors used as pass elements associated with general purpose drivers. Embodiments herein prevent excessive steady-state current flow through one or more driver pass elements and/or through load elements in series with the pass element(s) via a current sensing and driver preamplifier feedback loop. A transient over-current protection circuit includes a fast transient switch and a transient over-current control circuit. The transient over-current control circuit rectifies one or more transient voltage spikes to create a momentary direct current (DC) voltage power supply (MVS) to power a fast transient driver circuit and to trip the fast transient switch. The fast transient switch discharges a transient pass element input voltage (e.g.

Abstract: An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so as to receive from the pin a current to be controlled. There is a second MOS transistor coupled with a gate to the common gate node, with a source to ground and with a drain so as to receive a reference current controlled by a control loop. There is a first resistor coupled between the common gate node and ground.

Abstract: An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so as to receive from the pin a current to be controlled. There is a second MOS transistor coupled with a gate to the common gate node, with a source to ground and with a drain so as to receive a reference current controlled by a control loop. There is a first resistor coupled between the common gate node and ground.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: A delay locked loop (DLL) architecture includes a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: A delay locked loop (DLL) architecture includes a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.

Abstract: The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.

Abstract: The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit.