Abstract: A successive approximation analog-to-digital converter includes a digital-to-analog converter DAC configured to receive a digital signal. First conversion units of the DAC are configured to sample an analog signal via a first switch and provide a first level voltage. Each first conversion unit includes a first capacitor array and a first switch array controlled from the digital signal. A single second conversion unit of the DAC is configured to provide a second level voltage. The second conversion unit includes a second capacitor array and a second switch array. A comparator operates to compare each of the first level voltages to the second level voltage and to provide a comparison signal based on each comparison and actuation of a set of third switches. A control circuit closes the first switches simultaneously and closes the third switches successively for the conversion of each sampled analog signal.

Abstract: According to one aspect, an ambient-light sensor includes a photodiode configured to generate an electrical signal according to an ambient light, a capacitive-feedback transimpedance amplifier connected at its input to the photodiode for receiving a signal generated by the photodiode and for generating as an output an amplified signal from the signal generated by the photodiode, and an auto-zero switch at the input of the capacitive-feedback transimpedance amplifier. The ambient-light sensor further includes a control circuit including a bootstrap circuit configured to receive an initial positive- or zero-voltage logic control signal, and then generate, from this initial logic control signal, an adapted logic control signal having a first positive voltage level and a second negative voltage control level for controlling the auto-zero switch.

Abstract: A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.

Abstract: According to one aspect, an ambient-light sensor includes a photodiode configured to generate an electrical signal according to an ambient light, a capacitive-feedback transimpedance amplifier connected at its input to the photodiode for receiving a signal generated by the photodiode and for generating as an output an amplified signal from the signal generated by the photodiode, and an auto-zero switch at the input of the capacitive-feedback transimpedance amplifier. The ambient-light sensor further includes a control circuit including a bootstrap circuit configured to receive an initial positive- or zero-voltage logic control signal, and then generate, from this initial logic control signal, an adapted logic control signal having a first positive voltage level and a second negative voltage control level for controlling the auto-zero switch.

Abstract: A successive approximation analog-to-digital converter includes a digital-to-analog converter DAC configured to receive a digital signal. First conversion units of the DAC are configured to sample an analog signal via a first switch and provide a first level voltage. Each first conversion unit includes a first capacitor array and a first switch array controlled from the digital signal. A single second conversion unit of the DAC is configured to provide a second level voltage. The second conversion unit includes a second capacitor array and a second switch array. A comparator operates to compare each of the first level voltages to the second level voltage and to provide a comparison signal based on each comparison and actuation of a set of third switches. A control circuit closes the first switches simultaneously and closes the third switches successively for the conversion of each sampled analog signal.

Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.

Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.

Abstract: This application relates to modulators for providing time-encoded signals and in particular PWM signals. A modulator (200) has a first controlled oscillator (201P) configured to receive a first oscillator driving signal and output a first oscillation signal (S1). An accumulator (204) is configured to provide an accumulator value (VAL) based on a number of pulses of the first oscillation signal and a hysteretic comparator (205) alternates between first and second output states based on a hysteretic comparison of the accumulator value with a defined reference (REF). The first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator.

Abstract: This application relates to modulators for providing time-encoded signals and in particular PWM signals. A modulator (200) has a first controlled oscillator (201P) configured to receive a first oscillator driving signal and output a first oscillation signal (S1). An accumulator (204) is configured to provide an accumulator value (VAL) based on a number of pulses of the first oscillation signal and a hysteretic comparator (205) alternates between first and second output states based on a hysteretic comparison of the accumulator value with a defined reference (REF). The first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator.

Abstract: This application relates to modulators for providing time-encoded signals and in particular PWM signals. A modulator (200) has a first controlled oscillator (201P) configured to receive a first oscillator driving signal and output a first oscillation signal (S1). An accumulator (204) is configured to provide an accumulator value (VAL) based on a number of pulses of the first oscillation signal and a hysteretic comparator (205) alternates between first and second output states based on a hysteretic comparison of the accumulator value with a defined reference (REF). The first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator.

Abstract: A device may be associated with a power source. The device may include a charge pump configured to output a pulse-width modulated voltage based upon an input voltage from the power source, with the pulse-width modulated voltage varying between a first voltage and a second voltage. The device may also include a low-pass filter comprising an output capacitor, with the output capacitor being configured to average the pulsed-width modulated voltage and to output a filtered voltage having a value different than that of the input voltage. The device may further include a controller configured to selectively decouple the charge pump from the power source when a load imposed on the low-pass filter is below a threshold load.

Abstract: A device may be associated with a power source. The device may include a charge pump configured to output a pulse-width modulated voltage based upon an input voltage from the power source, with the pulse-width modulated voltage varying between a first voltage and a second voltage. The device may also include a low-pass filter comprising an output capacitor, with the output capacitor being configured to average the pulsed-width modulated voltage and to output a filtered voltage having a value different than that of the input voltage. The device may further include a controller configured to selectively decouple the charge pump from the power source when a load imposed on the low-pass filter is below a threshold load.