Patents by Inventor Sridevan Parameswaran
Sridevan Parameswaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10740674Abstract: A method of configuring a System-on-Chip (SoC) to execute a Convolutional Neural Network (CNN) by (i) receiving scheduling schemes each specifying a sequence of operations executable by Processing Units (PUs) of the SoC; (ii) selecting, a scheduling scheme for a current layer of the CNN; (iii) determining a current state of memory for a storage location in the SoC allocated for storing feature map data from the CNN; (iv) selecting, from the plurality of scheduling schemes and dependent upon the scheduling scheme for the current layer of the CNN, a set of candidate scheduling schemes for a next layer of the CNN; and (v) selecting, from the set of candidate scheduling schemes dependent upon the determined current state of memory, a scheduling scheme for the next layer of the CNN.Type: GrantFiled: May 25, 2017Date of Patent: August 11, 2020Assignee: Canon Kabushiki KaishaInventors: Jude Angelo Ambrose, Iftekhar Ahmed, Yusuke Yachide, Haseeb Bokhari, Jorgen Peddersen, Sridevan Parameswaran
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Patent number: 10684776Abstract: A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication between processors of the heterogeneous multi-processor system. For each subgraph the method (i) determines a plurality of subgraph design points. Each subgraph design point has a variation of channel mapping between any two of the processors in the subgraph by selecting from first-in-first-out (FIFO) memory and shared cache, and varying the shared cache and a local memory associated with at least one of the processors according to the channel mapping; and (ii) selects a memory solution for the subgraph, based on a cost associated with the selected memory solution. The method then determines a configuration for the graph of the heterogeneous multi-processor system, based on the selected memory solutions, to determine the configuration for inter-processor communication for the heterogeneous multi-processor system.Type: GrantFiled: June 10, 2015Date of Patent: June 16, 2020Assignee: CANON KABUSHIKI KAISHAInventors: Kapil Batra, Yusuke Yachide, Haris Javaid, Sridevan Parameswaran, Su Myat Min Shwe
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Patent number: 10664310Abstract: A method of configuring a System on Chip to execute a CNN process comprising CNN layers, the method comprising, for each schedule: determining memory access amount information describing how many memory accesses are required; expressing the memory access amount information as relationships describing reusability of data; combining the relationships with a cost of writing and reading from external memory, to form memory access information; determining a memory allocation for on-chip memory of the SoC for the input FMs and the output FMs; and determining, dependent upon the memory access information and the memory allocation for each schedule; a schedule which minimises the memory access information of external memory access for the CNN layer of the CNN process; and a memory allocation associated with the determined schedule.Type: GrantFiled: December 14, 2018Date of Patent: May 26, 2020Assignee: Canon Kabushiki KaishaInventors: Haseeb Bokhari, Jorgen Peddersen, Sridevan Parameswaran, Iftekhar Ahmed, Yusuke Yachide
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Publication number: 20190187963Abstract: A method of configuring a System on Chip to execute a CNN process comprising CNN layers, the method comprising, for each schedule: determining memory access amount information describing how many memory accesses are required; expressing the memory access amount information as relationships describing reusability of data; combining the relationships with a cost of writing and reading from external memory, to form memory access information; determining a memory allocation for on-chip memory of the SoC for the input FMs and the output FMs; and determining, dependent upon the memory access information and the memory allocation for each schedule; a schedule which minimises the memory access information of external memory access for the CNN layer of the CNN process; and a memory allocation associated with the determined schedule.Type: ApplicationFiled: December 14, 2018Publication date: June 20, 2019Inventors: HASEEB BOKHARI, JORGEN PEDDERSEN, SRIDEVAN PARAMESWARAN, IFTEKHAR AHMED, YUSUKE YACHIDE
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Publication number: 20170344882Abstract: A method of configuring a System-on-Chip (SoC) to execute a Convolutional Neural Network (CNN) by (i) receiving scheduling schemes each specifying a sequence of operations executable by Processing Units (PUs) of the SoC; (ii) selecting, a scheduling scheme for a current layer of the CNN; (iii) determining a current state of memory for a storage location in the SoC allocated for storing feature map data from the CNN; (iv) selecting, from the plurality of scheduling schemes and dependent upon the scheduling scheme for the current layer of the CNN, a set of candidate scheduling schemes for a next layer of the CNN; and (v) selecting, from the set of candidate scheduling schemes dependent upon the determined current state of memory, a scheduling scheme for the next layer of the CNN.Type: ApplicationFiled: May 25, 2017Publication date: November 30, 2017Inventors: JUDE ANGELO AMBROSE, IFTEKHAR AHMED, YUSUKE YACHIDE, HASEEB BOKHARI, JORGEN PEDDERSEN, SRIDEVAN PARAMESWARAN
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Patent number: 9477799Abstract: A method of determining a metric of a System-on-Chip (SoC), the method comprising: receiving a model dependency graph representing the SoC, the model dependency graph having a plurality of nodes representing components of the SoC and their models, and a plurality of directed edges between the nodes representing variables passed between the nodes of the model dependency graph; modifying the model dependency graph by clustering a plurality of strongly connected nodes in the model dependency graph into a single clustered node to form a clustered model dependency graph; determining an execution schedule according to a direction of an edge in the clustered model dependency graph; and executing models in the clustered model dependency graph according to the execution schedule to determine metrics of the SoC.Type: GrantFiled: November 26, 2014Date of Patent: October 25, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Yusuke Yachide, Haris Javaid, Sridevan Parameswaran
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Publication number: 20150363110Abstract: A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication between processors of the heterogeneous multi-processor system. For each subgraph the method (i) determines a plurality of subgraph design points. Each subgraph design point has a variation of channel mapping between any two of the processors in the subgraph by selecting from first-in-first-out (FIFO) memory and shared cache, and varying the shared cache and a local memory associated with at least one of the processors according to the channel mapping; and (ii) selects a memory solution for the subgraph, based on a cost associated with the selected memory solution. The method then determines a configuration for the graph of the heterogeneous multi-processor system, based on the selected memory solutions, to determine the configuration for inter-processor communication for the heterogeneous multi-processor system.Type: ApplicationFiled: June 10, 2015Publication date: December 17, 2015Inventors: KAPIL BATRA, Yusuke Yachide, Haris Javaid, Sridevan Parameswaran, Su Myat Min Shwe
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Publication number: 20150154330Abstract: A method of determining a metric of an SoC, the method comprising: receiving a model dependency graph representing the SoC, the model dependency graph having a plurality of nodes representing components of the SoC and their models, and a plurality of directed edges between the nodes representing variables passed between the nodes of the model dependency graph; modifying the model dependency graph by clustering a plurality of strongly connected nodes in the model dependency graph into a single clustered node to form a clustered model dependency graph; determining an execution schedule according to a direction of an edge in the clustered model dependency graph; and executing models in the clustered model dependency graph according to the execution schedule to determine metrics of the SoC.Type: ApplicationFiled: November 26, 2014Publication date: June 4, 2015Inventors: YUSUKE YACHIDE, Haris JAVAID, SRIDEVAN PARAMESWARAN
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Patent number: 8018928Abstract: A method for processing a packet comprising an ordered sequence of packet parts is disclosed. The method uses a set of hardware processing modules, and the method comprises the steps of broadcasting, in a step the next header field of a received packet part to the set of processing modules, and processing, in a step the received packet part by a sub-set of the modules dependent upon the broadcast next header field.Type: GrantFiled: November 19, 2004Date of Patent: September 13, 2011Assignee: Canon Kabushiki KaishaInventors: Sridevan Parameswaran, Jorgen Peddersen, Ashley Partis
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Patent number: 7672694Abstract: An architecture for selectively powering a receive module (108) is disclosed. The architecture comprises the receive module (108) which is functionally adapted, while power is applied to the receive module (108) by a power module (601), and after a power-up time interval has elapsed, to process a traffic packet. The architecture further comprises the power module (601) that is adapted to apply power to the receive module 108 dependent upon arrival of a wake-up packet.Type: GrantFiled: June 30, 2004Date of Patent: March 2, 2010Assignee: Canon Kabushiki KaishaInventors: Sridevan Parameswaran, Jorgen Peddersen, Ashley Partis
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Publication number: 20050007972Abstract: An architecture for selectively powering a receive module (108) is disclosed. The architecture comprises the receive module (108) which is functionally adapted, while power is applied to the receive module (108) by a power module (601), and after a power-up time interval has elapsed, to process a traffic packet. The architecture further comprises the power module (601) that is adapted to apply power to the receive module 108 dependent upon arrival of a wake-up packet.Type: ApplicationFiled: June 30, 2004Publication date: January 13, 2005Applicant: CANON KABUSHIKI KAISHAInventors: Sridevan Parameswaran, Jorgen Peddersen, Ashley Partis