Patents by Inventor Sridhar Balakrishnan
Sridhar Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230281429Abstract: Existing machine learning systems require historical data to perform analytics to detect faults in a machine and are unable to detect new types of faults/changes occurring in real time. These systems further fail to identify operation changes due to sensor drift and forget past events that have occurred. Present application provides systems and methods for identifying and classifying sensor drifts and diverse varying operational conditions from continually received sensor data using continual training of variational autoencoders (VAE) following drift specific characteristics, wherein sensor drift is compensated based on identified changes in sensors and degradation in machine(s).Type: ApplicationFiled: January 5, 2023Publication date: September 7, 2023Applicant: Tata Consultancy Services LimitedInventors: Soma Bandyopadhyay, Sridhar Balakrishnan, Shruti Sachan, Yasasvy Tadepalli, Arpan Pal, Anish Datta, Karthik Leburi, Srinivas Raghu Raman Gadepally
-
Publication number: 20220059484Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
-
Patent number: 11201129Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: GrantFiled: February 22, 2019Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
-
Publication number: 20190198472Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: ApplicationFiled: February 22, 2019Publication date: June 27, 2019Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
-
Patent number: 10249588Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: GrantFiled: December 5, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
-
Publication number: 20170084564Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: ApplicationFiled: December 5, 2016Publication date: March 23, 2017Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
-
Patent number: 9543261Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: GrantFiled: December 20, 2010Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
-
Publication number: 20160307796Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Hui Jae Yoo, Jeffery D. Bielefeld, Sean W. King, Sridhar Balakrishnan
-
Patent number: 9461010Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.Type: GrantFiled: January 18, 2016Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Andryushchenko, Guanghai Xu
-
Publication number: 20160133596Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.Type: ApplicationFiled: January 18, 2016Publication date: May 12, 2016Applicant: Intel CorporationInventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Andryushchenko, Guanghai Xu
-
Patent number: 9269686Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.Type: GrantFiled: December 18, 2013Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana T. Adryushchenko, Guanghai Xu
-
Publication number: 20140106560Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Inventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Tanya Andryushcheko, Guanghai Xu
-
Patent number: 8637778Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.Type: GrantFiled: April 8, 2010Date of Patent: January 28, 2014Assignee: Intel CorporationInventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Tanya Andryushchenko, Guanghai Xu
-
Patent number: 8580679Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: GrantFiled: August 20, 2007Date of Patent: November 12, 2013Assignee: Intel CorporationInventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
-
Publication number: 20130260553Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.Type: ApplicationFiled: May 13, 2013Publication date: October 3, 2013Inventors: Hui Jae Yoo, Jeffrey D. Bielefeld, Sean W. King, Sridhar Balakrishnan
-
Patent number: 8508018Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.Type: GrantFiled: September 24, 2010Date of Patent: August 13, 2013Assignee: Intel CorporationInventors: Rohan N. Akolkar, Sridhar Balakrishnan, James S. Clarke, Christopher J. Jezewski, Philip Yashar
-
Patent number: 8461683Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.Type: GrantFiled: April 1, 2011Date of Patent: June 11, 2013Assignee: Intel CorporationInventors: Hui Jae Yoo, Jeffery D. Bielefeld, Sean W. King, Sridhar Balakrishnan
-
Publication number: 20120248608Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.Type: ApplicationFiled: April 1, 2011Publication date: October 4, 2012Inventors: Hui Jae Yoo, Jeffery D. Bielefeld, Sean W. King, Sridhar Balakrishnan
-
Publication number: 20120077053Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: Rohan N. Akolkar, Sridhar Balakrishnan, James S. Clarke, Christopher J. Jezewski, Philip Yashar
-
Publication number: 20110247872Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.Type: ApplicationFiled: April 8, 2010Publication date: October 13, 2011Inventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Tanya Andryushchenko, Guanghai Xu