Abstract: A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

Abstract: The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path.

Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

Abstract: A data channel controller, coupleable to a base computer system including a base memory, for managing the transport of multiple data streams through a base system interface including a first buffer, a pool memory including a plurality of second buffers, and one or more peripheral devices each having a third buffer. An arbiter system is coupled to said pool memory for selectively enabling the transfer of data with respect to a predetermined first buffer in response to first and second request signals. The peripheral devices operate to transport data through their third buffers with respect to a peripheral interfaces characterized as each having a predetermined data transfer rate. The peripheral devices first request signals to the arbiter system under first predetermined conditions with respect to the presence of data in corresponding third buffers to obtain a transfer of data between corresponding second and third buffers.

Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

Abstract: A multiple data stream channel controller providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel coupled between a general purpose processor system and a special purpose processor system. The controller comprises a first bus master interface coupleable to a general purpose processor system bus, a second bus master interface coupleable to a special purpose processor system bus, a segmentable buffer memory and a controller that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to a plurality of signals provided by the special purpose processor bus to request transfer of successive data segments from a respective plurality of data streams staged in the segmentable buffer memory.

Abstract: A data transfer control system including a pool memory, a plurality of peripheral devices, and a transfer controller. The pool memory provides for the storage of data in a plurality of FIFOs formed within the pool memory. The plurality of peripheral devices are coupleable to the pool memory to provide for the transfer of data between programmatically associated FIFOs and peripheral devices. The transfer controller is coupled to the pool memory and to the peripheral devices for selectively managing the transfer of data between the FIFOs and the peripheral devices. The transfer controller includes a distributed signaling system coupled to the peripheral devices to permit the broadcast of status information reflective of a transfer of data relative to a predetermined FIFO to the peripheral devices.

Abstract: A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data tranfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.

Abstract: A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.

Abstract: A system and method for managing the reserved memory in a microcomputer copies selected portions of reserved memory to a new reserved memory having a faster access time, and allows any free portions of the new reserved memory to be accessed by a typical software application. After the selected portions of reserved memory are copied, all access to an address within a selected portion are re-directed to the new reserved memory. Any free portions of new reserved memory have additional, accessible memory re-mapped to these free portions.

Abstract: A system and method for managing the reserved memory in a microcomputer copies selected portions of reserved memory to a new reserved memory having a faster access time, and allows any free portions of the new reserved memory to be accessed by a typical software application. After the selected portions of reserved memory are copied, all access to an address within a selected portion are re-directed to the new reserved memory. Any free portions of new reserved memory have additional, accessible memory re-mapped to these free portions.