Abstract: An input circuit that recognizes (e.g., buffers) logic level signals (e.g., of an input signal) represented by voltage levels that are lower than a supply voltage of an input circuit, and that exhibits static current draw immunity during stable states of an input signal. In one or more examples, series inverters are provided to buffer an input node and an output node of the input circuit. A voltage domain at the input circuit or output node may be higher than a voltage domain at the input node. Power supply to a first inverter of the series inverters may be turned OFF at least partially responsive to an indication that an output signal is a logic high; and power supply to the first inverter of the series inverters may be turned ON at least partially responsive to an indication that the output signal is a logic low.

Abstract: A memory device comprises memory elements that are arranged in an array. The array includes rows associated with wordlines and columns associated with bitlines. The memory elements in a row share a wordline and memory elements in a column share a bitline. For each wordline, a wordline driver circuit is associated with the wordline. The memory device comprises a boost circuit that has an output coupled to the wordline driver circuits. The boost circuit is configured to provide a negative voltage to the wordlines during a read operation of the memory device such that unselected wordlines are held at a negative voltage below a ground potential while a selected wordline is held at a supply voltage during the read operation.

Abstract: A memory device comprises memory elements that are arranged in an array. The array includes rows associated with wordlines and columns associated with bitlines. The memory elements in a row share a wordline and memory elements in a column share a bitline. For each wordline, a wordline driver circuit is associated with the wordline. The memory device comprises a boost circuit that has an output coupled to the wordline driver circuits. The boost circuit is configured to provide a negative voltage to the wordlines during a read operation of the memory device such that unselected wordlines are held at a negative voltage below a ground potential while a selected wordline is held at a supply voltage during the read operation.

Abstract: A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current.

Abstract: A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current.