Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.

Abstract: An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.

Abstract: An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.

Abstract: A computer-implemented method for modifying an original design of an integrated circuit in accordance with an engineering change order (ECO) design includes cloning complex logic gate having multiple logic functions with cloned logic gates in parallel with the corresponding complex logic gates in the original design and the ECO design and expanding each cloned logic gate to corresponding base functionality logic gates to provide an expanded original design and an expanded ECO design using the processor. The method also includes modifying at least a portion of the expanded original design to have a circuit topology that is the same as the expanded ECO design in order to have an input from the expanded original design to an output structure be the same as the input from the expanded ECO design to the output structure in response to an expanded original design input and an expanded ECO design input being non-equivalent.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Abstract: A method, executed by a computer, includes receiving a scan chain design comprising a plurality of parallel scan chains, each parallel scan chain comprising one or more serially connected single-bit registers, each parallel scan chain having a scan chain length. The plurality of parallel scan chains are interspersed with a plurality of stumpmuxes that enable access to the plurality of parallel scan chains and segment each parallel scan chain into a plurality of scan chain segments. The method further includes conducting a determining operation comprising determining a parallel scan chain having a longest scan chain length, and conducting a swapping operation comprising swapping scan chain segments attached to a selected stumpmux to reduce the longest scan chain length and produce an updated scan chain design. A computer system and computer product corresponding to the above method are also disclosed herein.

Abstract: A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.

Abstract: A computer-implemented method for modifying an original design of an integrated circuit in accordance with an engineering change order (ECO) design includes cloning complex logic gate having multiple logic functions with cloned logic gates in parallel with the corresponding complex logic gates in the original design and the ECO design and expanding each cloned logic gate to corresponding base functionality logic gates to provide an expanded original design and an expanded ECO design using the processor. The method also includes modifying at least a portion of the expanded original design to have a circuit topology that is the same as the expanded ECO design in order to have an input from the expanded original design to an output structure be the same as the input from the expanded ECO design to the output structure in response to an expanded original design input and an expanded ECO design input being non-equivalent.

Abstract: A method, executed by a computer, includes receiving a scan chain design comprising a plurality of parallel scan chains, each parallel scan chain comprising one or more serially connected single-bit registers, each parallel scan chain having a scan chain length. The plurality of parallel scan chains are interspersed with a plurality of stumpmuxes that enable access to the plurality of parallel scan chains and segment each parallel scan chain into a plurality of scan chain segments. The method further includes conducting a determining operation comprising determining a parallel scan chain having a longest scan chain length, and conducting a swapping operation comprising swapping scan chain segments attached to a selected stumpmux to reduce the longest scan chain length and produce an updated scan chain design. A computer system and computer product corresponding to the above method are also disclosed herein.

Abstract: A method, executed by a computer, includes receiving a scan chain design comprising a plurality of parallel scan chains, each parallel scan chain comprising one or more serially connected single-bit registers, each parallel scan chain having a scan chain length. The plurality of parallel scan chains are interspersed with a plurality of stumpmuxes that enable access to the plurality of parallel scan chains and segment each parallel scan chain into a plurality of scan chain segments. The method further includes conducting a determining operation comprising determining a parallel scan chain having a longest scan chain length, and conducting a swapping operation comprising swapping scan chain segments attached to a selected stumpmux to reduce the longest scan chain length and produce an updated scan chain design. A computer system and computer product corresponding to the above method are also disclosed herein.

Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.

Abstract: A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor chips is disclosed. The TSVAD may include a switching circuit, having a conductive pad terminal, a TSV terminal, an input terminal coupled to a sending logic circuit, an output terminal coupled to a receiving logic circuit, and logic devices to, in response to control signals, couple the TSV terminal to the conductive pad terminal, in one configuration, and couple the TSV terminal to another terminal in another configuration. The TSVAD may also include a control circuit to generate control signals to cause an input selection circuit to drive a signal from the sending logic circuit onto the input terminal, and to cause an output selection circuit to drive a logic signal from the output terminal to the receiving logic circuit.