Abstract: Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for advanced register merging. A first register-merging operation may be configured to merge, into a first survivor register, a first plurality of registers of the RTL description. A second register-merging operation configured to merge, into a first equivalence class, a second plurality of registers that share a first functional equivalency based on output of the first register-merging operation. Any register in the first equivalence class as noted here may in turn be non-equivalent to any register in the second equivalence class. Equivalence of registers in a given class may be verified using simulations or satisfiability checks.

Abstract: Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.

Abstract: Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.

Abstract: In an embodiment of the present invention there is provided a method of facilitating pipelines throughput in a pipeline processor system including at least one producer processor/consumer processor pair. The method includes the step of controlling (22) the producer processor/consumer processor pair to allow them to run out-of-sync without violating dependency (21,23,26).

Abstract: In an embodiment of the present invention there is provided a method of facilitating pipelines throughput in a pipeline processor system including at least one producer processor/consumer processor pair. The method includes the step of controlling (22) the producer processor/consumer processor pair to allow them to run out-of-sync without violating dependency (21,23,26).