Abstract: A system and method for efficiently allocating resources of destinations to sources conveying requests to the destinations. In various embodiments, a computing system includes multiple sources that generate requests and multiple destinations that service the requests. One or more transaction tables store requests received from the multiple sources. Arbitration logic selects requests and stores them in a processing table. When the logic selects a given request from the processing table, and determines resources for the corresponding destination is unavailable, the logic removes the given request from the processing table and allocates the request in a retry handling queue. When the retry handling queue has no data storage for the request, logic updates a transaction table entry and maintains a count of such occurrences. When the count exceeds a threshold, the logic stalls requests for that source. Requests in the retry handling queue have priority over requests in the transaction tables.

Abstract: Systems, apparatuses, and methods for performing coherence processing and memory cache processing in parallel are disclosed. A system includes a communication fabric and a plurality of dual-processing pipelines. Each dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. The communication fabric forwards a transaction to a given dual-processing pipeline, with the communication fabric selecting the given dual-processing pipeline, from the plurality of dual-processing pipelines, based on a hash of the address of the transaction. The given dual-processing pipeline performs a duplicate tag lookup in parallel with a memory cache tag lookup for the transaction. By performing the duplicate tag lookup and the memory cache tag lookup in a parallel fashion rather than in a serial fashion, latency and power consumption are reduced while performance is enhanced.

Abstract: Systems, apparatuses, and methods for implementing a distributed global ordering point are disclosed. A system includes at least a communication fabric, sequencing logic, and a plurality of coherence point pipelines. Each coherence point pipeline receives transactions from the communication fabric and then performs coherence operations and a memory cache lookup for the received transactions. The global ordering point of the system is distributed across the outputs of the separate coherence point pipelines. Device-ordered transactions travelling upstream toward memory are assigned sequence numbers by the sequencing logic. The transactions are speculatively issued from the communication fabric to the coherence point pipelines. Speculatively issuing the transactions to the coherence point pipelines may cause the transactions to pass through the distributed global ordering point out of order. Control logic on the downstream path reorders the transactions based on the assigned sequence numbers.

Abstract: A system and method for efficiently allocating resources of destinations to sources conveying requests to the destinations. In various embodiments, a computing system includes multiple sources that generate requests and multiple destinations that service the requests. One or more transaction tables store requests received from the multiple sources. Arbitration logic selects requests and stores them in a processing table. When the logic selects a given request from the processing table, and determines resources for the corresponding destination is unavailable, the logic removes the given request from the processing table and allocates the request in a retry handling queue. When the retry handling queue has no data storage for the request, logic updates a transaction table entry and maintains a count of such occurrences. When the count exceeds a threshold, the logic stalls requests for that source. Requests in the retry handling queue have priority over requests in the transaction tables.

Abstract: A memory cache controller includes a transaction arbiter circuit and a retry queue circuit. The transaction arbiter circuit may determine whether a received memory transaction can currently be processed by a transaction pipeline. The retry queue circuit may queue memory transactions that the transaction arbiter circuit determines cannot be processed by the transaction pipeline. In response to receiving a memory transaction that is a cache management transaction, the retry queue circuit may establish a dependency from the cache management transaction to a previously stored memory transaction in response to a determination that both the previously stored memory transaction and the cache management transaction target a common address. Based on the dependency, the retry queue circuit may initiate a retry, by the transaction pipeline, of one or more of the queued memory transactions in the retry queue circuit.

Abstract: Systems, apparatuses, and methods for implementing a distributed global ordering point are disclosed. A system includes at least a communication fabric, sequencing logic, and a plurality of coherence point pipelines. Each coherence point pipeline receives transactions from the communication fabric and then performs coherence operations and a memory cache lookup for the received transactions. The global ordering point of the system is distributed across the outputs of the separate coherence point pipelines. Device-ordered transactions travelling upstream toward memory are assigned sequence numbers by the sequencing logic. The transactions are speculatively issued from the communication fabric to the coherence point pipelines. Speculatively issuing the transactions to the coherence point pipelines may cause the transactions to pass through the distributed global ordering point out of order. Control logic on the downstream path reorders the transactions based on the assigned sequence numbers.

Abstract: Systems, apparatuses, and methods for performing coherence processing and memory cache processing in parallel are disclosed. A system includes a communication fabric and a plurality of dual-processing pipelines. Each dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. The communication fabric forwards a transaction to a given dual-processing pipeline, with the communication fabric selecting the given dual-processing pipeline, from the plurality of dual-processing pipelines, based on a hash of the address of the transaction. The given dual-processing pipeline performs a duplicate tag lookup in parallel with a memory cache tag lookup for the transaction. By performing the duplicate tag lookup and the memory cache tag lookup in a parallel fashion rather than in a serial fashion, latency and power consumption are reduced while performance is enhanced.

Abstract: A memory cache controller includes a transaction arbiter circuit and a retry queue circuit. The transaction arbiter circuit may determine whether a received memory transaction can currently be processed by a transaction pipeline. The retry queue circuit may queue memory transactions that the transaction arbiter circuit determines cannot be processed by the transaction pipeline. In response to receiving a memory transaction that is a cache management transaction, the retry queue circuit may establish a dependency from the cache management transaction to a previously stored memory transaction in response to a determination that both the previously stored memory transaction and the cache management transaction target a common address.

Abstract: An embodiment of an apparatus includes a retry queue circuit, a transaction arbiter circuit, and a plurality of transaction buffers. The retry queue circuit may store one or more entries corresponding to one or more memory transactions. A position in the retry queue circuit of an entry of the one or more entries may correspond to a priority for processing a memory transaction corresponding to the entry. The transaction arbiter circuit may receive a real-time memory transaction from a particular transaction buffer. In response to a determination that the real-time memory transaction is unable to be processed, the transaction arbiter circuit may create an entry for the real-time memory transaction in the retry queue circuit. In response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, the transaction arbiter circuit may upgrade the bulk memory transaction to use real-time memory resources.

Abstract: Longest Prefix Match (LPM) is implemented using a binary tree based search algorithm. Masked entries are stored in a plurality of binary search engines, wherein each of the binary search engines stores masked entries of a corresponding mask length. A search value is applied to each of the binary search engines in parallel. The search value is masked within each of the binary search engines, thereby creating a plurality of masked search values, each having a masked length equal to the mask length of the corresponding binary search engine. Each of the masked search values is compared with the masked entries of the corresponding binary search engine. An LPM result is selected from the binary search engine that detects a match, and has the longest corresponding mask length. Alternately, each binary search engine stores masked entries of N mask lengths, and N consecutive comparisons are performed to identify the LPM.

Abstract: Longest Prefix Match (LPM) is implemented using a binary tree based search algorithm. Masked entries are stored in a plurality of binary search engines, wherein each of the binary search engines stores masked entries of a corresponding mask length. A search value is applied to each of the binary search engines in parallel. The search value is masked within each of the binary search engines, thereby creating a plurality of masked search values, each having a masked length equal to the mask length of the corresponding binary search engine. Each of the masked search values is compared with the masked entries of the corresponding binary search engine. An LPM result is selected from the binary search engine that detects a match, and has the longest corresponding mask length. Alternately, each binary search engine stores masked entries of N mask lengths, and N consecutive comparisons are performed to identify the LPM.

Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform(DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Abstract: The present invention allows a single display controller design to be used in multiple markets by providing an additional stand-alone circuit which converts conventional analog CRT display signals to digital flat panel display or other digital display signals. A single VGA CRT controller may be implemented in both desktop and portable (e.g., laptop) markets thereby reducing the cost of the display controller through the economies of scale. For a laptop or other digital display markets, the apparatus of the present invention may be applied to a conventional analog CRT controller to convert analog CRT signals to digital laptop signals to generate a display on a flat panel display or other digital device. In addition, the apparatus of the present invention may be incorporated into a stand-alone flat panel display intended for use as a replacement for conventional CRT monitors. The apparatus of the present invention accepts a conventional analog CRT input and outputs digital flat panel display signals.

Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g.

Abstract: The present invention allows a single display controller design to be used in multiple markets by providing an additional stand-alone circuit which converts conventional analog CRT display signals to digital flat panel display or other digital display signals. A single VGA CRT controller may be implemented in both desktop and portable (e.g., laptop) markets thereby reducing the cost of the display controller through the economies of scale. For a laptop or other digital display markets, the apparatus of the present invention may be applied to a conventional analog CRT controller to convert analog CRT signals to digital laptop signals to generate a display on a flat panel display or other digital device. In addition, the apparatus of the present invention may be incorporated into a stand-alone flat panel display intended for use as a replacement for conventional CRT monitors. The apparatus of the present invention accepts a conventional analog CRT input and outputs digital flat panel display signals.

Abstract: A display controller in a computer system controls the output of graphics display data in a computer system having a fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a Discrete Time Oscillator (DTO) based clock divider and DCT based polyphase interpolation to upscale graphics display data from a first resolution to the panel resolution. DTO clock divider circuit synchronizes scan clocks between the input resolution and the desired output resolution. Within graphics display area, MVA.TM. display at greater color depth and resolution may be accommodated by additional DTO divider and interpolation steps.