Abstract: A system, platform, program product, and/or method for protecting sensitive data including decrypting an incoming message comprising a base message and the sensitive electronic data; removing the sensitive electronic data from the incoming message to create a stripped message; encrypting the sensitive electronic data; storing the encrypted sensitive electronic data in In-Memory Cache; and permitting the stripped message to be further processed without the sensitive electronic data. The system, platform, program product and/or method in an embodiment further includes: retrieving from the In-Memory Cache the encrypted sensitive electronic data; decrypting the encrypted sensitive electronic data retrieved from the In-Memory Cache; and injecting the sensitive electronic data into the stripped message.

Abstract: A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.

Abstract: Embodiment of the present invention relate to algorithms for computing the causal effect of position in search engine advertising listings on outcomes such as click-through rates and sales orders.

Abstract: A memory structure can include a first memory block including a plurality of memory cells corresponding to a first subset of addresses of a range of addresses and a second memory block including a plurality of memory cells corresponding to a second subset of addresses of the range of addresses. The memory structure can include control circuitry coupled to the first memory block and the second memory block and configured to provide control signals to the first memory block and the second memory block. The first memory block and the second memory block can be configured to implement a reduced power mode independently of one another responsive to the control signals.

Abstract: One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: In one embodiment, a method is provided for generating clock gating circuitry for a circuit design model. A Boolean expression of path sensitization is determined for each gate element in the netlist of a circuit design. For each gate element, a conjunction of the Boolean expression of the path sensitization and a Boolean expression of a disjunction of the observability conditions of one or more subsequent gates is determined to produce an intermediate Boolean expression. Intermediate Boolean expressions are backward retimed to produce the respective Boolean expression of the observability conditions of the each gate element. Clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements are generated and incorporated into the circuit design model.

Abstract: Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent limitations which make combinational equivalency checkers unable to prove equivalency of the two designs in a single step, a series of intermediate design transformations is introduced. These transformations are dependent on the techniques used in generating the power optimized design from the golden design, and may be generically described in a transformation language that provides the necessary constructs to specify an entire set of valid structural modifications.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element, wherein the first clock enable signal is generated to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: Embodiments of the present invention provide a method and apparatus for debugging an integrated circuit. In particular, one embodiment of the present invention includes steps of: (a) retrieving data from a design data base, and creating a design pattern in a pattern format, which design pattern includes stimulus data for stimuli to be applied to the integrated circuit and design response data for expected responses to the stimuli; (b) generating, responsive to the design pattern, a tester pattern and a test program for input to a tester; (c) testing the integrated circuit in the tester, responsive to the tester pattern and the test program, and generating a datalog that comprises test response data; and (d) generating a file, responsive to the datalog, wherein the test response data are reformatted into the pattern format.

Abstract: An electrical circuit includes a flip-flop, a first multiplexer, a second flip-flop, a third flip-flop, and output storage element including a second multiplexer and a fourth flip-flop. The first flip-flop, clocked functional clock signal, receives a functional signal. The first multiplexer receives the output of the first flip-flop and a test mode shift-in signal, and outputs one of them based on the state of a select input. The second flip-flop, clocked by a test clock signal, receives the output of the first multiplexer. The third flip-flop, clocked by a second test clock signal, receives the output of the second flip-flop. The second multiplexer receives the functional signal and the output of the third flip-flop, and outputs one of them based on a mode select input signal. The fourth flip-flop, clocked by a pulse-controlled functional clock signal, receives the output of the second multiplexer.

Abstract: Embodiments of the present invention provide a method and apparatus for debugging an integrated circuit. In particular, one embodiment of the present invention includes steps of: (a) retrieving data from a design data base, and creating a design pattern in a pattern format, which design pattern includes stimulus data for stimuli to be applied to the integrated circuit and design response data for expected responses to the stimuli; (b) generating, responsive to the design pattern, a tester pattern and a test program for input to a tester; (c) testing the integrated circuit in the tester, responsive to the tester pattern and the test program, and generating a datalog that comprises test response data; and (d) generating a file, responsive to the datalog, wherein the test response data are reformatted into the pattern format.