Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

Abstract: Provided is an architecture drift detection system and method including: obtaining a first set of architecture design metrics associated with a first application; obtaining first set of data metrics associated with a first instance of the first application that is installed at a first server computing system; obtaining a second set of data metrics associated with a second instance of the first application that is installed at a second server computing system; determining, using the first set of data metrics and the second set of data metrics, that at least one of the first instance, the first server computing system, the second instance, or the second server computing system deviates from one or more architecture design metrics from the first set of architecture design metrics associated with the first application; and providing a deviation notification indicating a deviation from the one or more architecture design metrics.

Abstract: Provided is an architecture drift detection system and method including: obtaining a first set of architecture design metrics associated with a first application; obtaining first set of data metrics associated with a first instance of the first application that is installed at a first server computing system; obtaining a second set of data metrics associated with a second instance of the first application that is installed at a second server computing system; determining, using the first set of data metrics and the second set of data metrics, that at least one of the first instance, the first server computing system, the second instance, or the second server computing system deviates from one or more architecture design metrics from the first set of architecture design metrics associated with the first application; and providing a deviation notification indicating a deviation from the one or more architecture design metrics.

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

Abstract: A process for recovering at least one metal from a metal containing resource, in particular containing at least one metal oxide. The process including the step: providing a crucible containing a chloride salt melt, at least one cathode and an anode connected to the salt melt, heating means for heating the salt melt, and an aluminum melt present at the bottom of the crucible, said aluminum melt forming a part of the anode.

Abstract: The invention concerns a process for recovering at least one rare earth metal (REM) from the group of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. A chloride salt melt is provided and aluminium chloride is used to chlorinate a REMcontaining resource. The REM can be recovered by electrolysis, vaporisation or hydrometallurgical methods.

Abstract: A method for producing a solid layer material (42), comprising providing (70) a first layer (30); providing (72) a second liquid layer (32) on the first layer (30); providing (74) a third liquid layer (34) on the second liquid layer (32), wherein the third liquid layer has a melting point that is higher than a melting point of the second liquid layer, and wherein the second liquid layer is between the first and third layers; cooling (76) a surface of the third liquid layer to a temperature less than the melting point of the third liquid layer; forming (78) the solid layer from the third liquid layer while cooling the third layer liquid; and removing (80) the solid layer.

Abstract: The invention relates to a method for the extraction of vanadium from various sources in the form of vanadiumpentoxide, V2O5, from a source containing vanadium. The method includes the steps of: providing a source of V2O5, heating the source to a temperature of at least 1000° C., evaporating V2O5 from the heated source and recovering the evaporated V2O5.

Abstract: A process for recovering at least one metal from a metal containing resource, in particular containing at least one metal oxide. The process including the step: providing a crucible containing a chloride salt melt, at least one cathode and an anode connected to the salt melt, heating means for heating the salt melt, and an aluminum melt present at the bottom of the crucible, said aluminum melt forming a part of the anode.

Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

Abstract: A method for producing a solid layer material (42), comprising providing (70) a first layer (30); providing (72) a second liquid layer (32) on the first layer (30); providing (74) a third liquid layer (34) on the second liquid layer (32), wherein the third liquid layer has a melting point that is higher than a melting point of the second liquid layer, and wherein the second liquid layer is between the first and third layers; cooling (76) a surface of the third liquid layer to a temperature less than the melting point of the third liquid layer; forming (78) the solid layer from the third liquid layer while cooling the third layer liquid; and removing (80) the solid layer.

Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

Abstract: Some embodiments of the present invention provide a system that verifies software which was distributed from a master site to a user site. During operation, the system receives a master list from the master site at the user site, where the master list specifies items of software which could be installed on the user site. The system also generates an actual list on the user site indicating which items of software are actually installed on the user site. The system then compares the actual list with the master list, and if the actual list is inconsistent with the master list, the system performs a remedial action.

Abstract: Some embodiments of the present invention provide a system for delivering software. During operation, the system receives selections from a user, wherein the selections specify items of software to be delivered from a master site to a user site. The system also receives priority information from the user, wherein the priority information specifies a priority for delivery for the selected items of software. Next, the system determines an order of delivery for the selected items of software based on the priority information. Finally, the system delivers the selected items of software from the master site to the user site in accordance with the determined order of delivery.

Abstract: The present invention provides methods and systems for controlling a catalytic process. The control system includes: an electroconductive support having a layer of a catalyst thereon; a first electrode in contact with said electroconductive support; a second electrode in contact with said catalyst layer; a current control unit for applying a current to said first and second electrodes and for controlling and varying the amount of current applied; an impedance measurement unit for continuously, monitoring and measuring the polarization impedance across an interface between the catalyst layer and the electroconductive support; a processing-unit for comparing the measured polarization impedance with a reference value. The amount of current applied to the catalyst layer and the electroconductive support via the first and second electrodes is varied to change the polarization impedance when the measured polarization impedance differs from the reference value.