Abstract: Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.

Abstract: An electronic device includes a plurality of hardware functional blocks, the hardware functional blocks being logically grouped into two or more islands, with each island including a different one or more of the hardware functional blocks. A hardware controller in the electronic device is configured to determine a present activity being performed by at least one of the hardware functional blocks. The hardware controller then, based on the present activity, configures supply voltages for the hardware functional blocks in some or all of the islands.

Abstract: An electronic device includes a plurality of hardware functional blocks, the hardware functional blocks being logically grouped into two or more islands, with each island including a different one or more of the hardware functional blocks. A hardware controller in the electronic device is configured to determine a present activity being performed by at least one of the hardware functional blocks. The hardware controller then, based on the present activity, configures supply voltages for the hardware functional blocks in some or all of the islands.

Abstract: Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.

Abstract: Various on-die-precision-resistor arrays, and methods of making and calibrating the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip and a precision resistor array on the semiconductor chip. A replica precision resistor array is on the semiconductor chip. The replica precision resistor array is configured to mimic the resistance behavior of the precision resistor array and has a characteristic resistance that is a function of temperature. The semiconductor chip is configured to calibrate the precision resistor array using the characterized resistance as a function of temperature, a resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature, and a temperature of the precision resistor array.

Abstract: A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.

Abstract: Systems, apparatuses, and methods for managing power usage of integrated circuits. One or more processor cores may be powered down when the system is idle. Even if there is no user activity, the processor core(s) may be woken up periodically for background downloads to retrieve the latest status for social media and other applications. Additionally, a power management unit may track the average number of active cores and the average core utilization. If the average number of active cores is less than a first threshold and the average core utilization is less than a second threshold, the power management unit may generate a request to offline one or more cores. Still further, when the processor's skin temperature is above a threshold and all of the cores are operating at the lowest acceptable operating point, one or more cores may be powered down.

Abstract: A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.

Abstract: A method includes adjusting a maximum skin temperature threshold of a device based on a device state, adjusting a power limit for the device based on the adjusted maximum skin temperature threshold, and operating the device based on the adjusted power limit. A processor includes a processing unit and a power management controller to adjust a maximum skin temperature threshold based on a device state and adjust a power limit for the processing unit based on the adjusted maximum skin temperature threshold.