Abstract: Systems, apparatuses and methods may provide for technology that identifies a NUMA node, defines a first virtual proximity domain within the NUMA node, and defines a second virtual proximity domain within the NUMA node, wherein the first virtual proximity domain and the second virtual proximity domain are defined via one or more OS interface tables.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receiving a sequence of transactions, each transaction including a request to write data to a memory device, processing the sequence of transactions, and communicating a response to a host after the sequence of transaction have been completed.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receiving a sequence of transactions, each transaction including a request to write data to a memory device, processing the sequence of transactions, and communicating a response to a host after the sequence of transaction have been completed.

Abstract: Examples include techniques for a write transaction to one or more memory devices maintained at a storage device. In some examples, the write transaction includes a disjointed atomic write transaction that includes a plurality of asynchronous write operations from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the disjointed atomic write transaction is associated with a multi-block transaction request initiated by the application or operating system that upon acceptance results in the plurality of asynchronous write operations to the storage device.

Abstract: Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete.

Abstract: A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (WB-E) memory space for an application running on the processing unit. The memory management system maps the WB-E memory space to the persistent memory. The application creates WB-E data by executing an instruction to store data to an address in the WB-E memory space. The WB-E data is automatically stored in a cache associated with the processing unit in response to creation of the WB-E data by the application. In response to execution of a commit instruction by the application after the application has created WB-E data for multiple memory addresses, the memory management system automatically ensures that all of the WB-E data for the application has been saved to the persistent memory domain. Other embodiments are described and claimed.

Abstract: Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete.

Abstract: A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (WB-E) memory space for an application running on the processing unit. The memory management system maps the WB-E memory space to the persistent memory. The application creates WB-E data by executing an instruction to store data to an address in the WB-E memory space. The WB-E data is automatically stored in a cache associated with the processing unit in response to creation of the WB-E data by the application. In response to execution of a commit instruction by the application after the application has created WB-E data for multiple memory addresses, the memory management system automatically ensures that all of the WB-E data for the application has been saved to the persistent memory domain. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology, and wherein the network adapter is configured to share a plurality of shared hardware components by limiting access to the air to one comm only at given time by designating one comm that owns the shared hardware components as a primary comm and all other comms are secondary comms, wherein the primary comm allows the secondary comms to use the shared hardware components when it is in an idle-state but when the primary comm returns from the idle state, it claims ownership of the shared resources and the secondary comms release the shared resources.

Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology, and wherein the network adapter is configured to share a plurality of shared hardware components by limiting access to the air to one comm only at given time by designating one comm that owns the shared hardware components as a primary comm and all other comms are secondary comms, wherein the primary comm allows the secondary comms to use the shared hardware components when it is in an idle-state but when the primary comm returns from the idle state, it claims ownership of the shared resources and the secondary comms release the shared resources.

Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology, and wherein the network adapter is configured to share a plurality of shared hardware components by limiting access to the air to one comm only at given time by designating one comm that owns the shared hardware components as a primary comm and all other comms are secondary comms, wherein the primary comm allows the secondary comms to use the shared hardware components when it is in an idle-state but when the primary comm returns from the idle state, it claims ownership of the shared resources and the secondary comms release the shared resources.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for autonomous memory subsystems in computing platforms. In some embodiments, the autonomous memory mechanism includes one or more autonomous memory logic instances (AMLs) and a transaction protocol to control the AMLs. The autonomous memory mechanism can be employed to accelerate bulk memory operations. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology, and wherein the network adapter is configured to share a plurality of shared hardware components by limiting access to the air to one comm only at given time by designating one comm that owns the shared hardware components as a primary comm and all other comms are secondary comms, wherein the primary comm allows the secondary comms to use the shared hardware components when it is in an idle-state but when the primary comm returns from the idle state, it claims ownership of the shared resources and the secondary comms release the shared resources.

Abstract: Processors, systems, and methods for virtual address translation by a processor for a peripheral device are disclosed. In one embodiment, a processor includes a memory management unit and an interface. The memory management unit is to translate a first address to a second address. The first address is an address usable by software to access the virtual memory space of the processor. The second address is an address usable by the processor to access the physical memory space of the processor. The interface is to receive the first address from a peripheral device, to receive a request to translate the first address, and to transmit the second address to the peripheral device for the peripheral device to use to access the physical memory space of the processor.

Abstract: Apparatus and systems, as well as methods and articles, may operate to measure a network link throughput value, compare the throughput value to a threshold value, and dynamically regulate the link speed based on the measured throughput value.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides in response to a command from an initiator device to a target device, generating a command context associated with the command, assigning a rule-based tag to the command, storing the command context in a command context queue, and forwarding a request having the command and the rule-based tag to a network device of the initiator device.