Patents by Inventor Sridharan Srivatsan

Sridharan Srivatsan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7690966
    Abstract: A method for planarizing a semiconductor substrate is provided. The method initiates with tracking a signal corresponding to a thickness of a conductive film disposed on the semiconductor substrate. Then, a second derivative is calculated from data representing the tracked signal. Next, the onset of planarization is identified based upon a change in the second derivative. A CMP system configured to identify a transition between stages of the CMP operation is also provided.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: April 6, 2010
    Assignee: Lam Research Corporation
    Inventors: Ramesh Gopalan, Sridharan Srivatsan, Katgenhalli Y. Ramanujam, Tom Ni, Conan Chiang
  • Publication number: 20090068767
    Abstract: A method for designing an etch recipe is provided. An etch is performed, comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over via. Via faceting is measured. The halogen to carbon ratio is reset according to the measured via faceting, where the halogen to carbon ratio is increased if too much faceting is measured and the halogen to carbon ratio is decreased if too little faceting is measured. The previous steps are repeated until a desired amount of faceting is obtained.
    Type: Application
    Filed: September 12, 2007
    Publication date: March 12, 2009
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Stephen Sirard, Mikio Nagai, Kenji Takeshita, Sridharan Srivatsan, Jungmin Ko
  • Patent number: 7413988
    Abstract: A method for planarizing a semiconductor substrate is provided. The method initiates with tracking a signal corresponding to a thickness of a conductive film disposed on the semiconductor substrate. Then, a second derivative is calculated from data representing the tracked signal. Next, the onset of planarization is identified based upon a change in the second derivative. A CMP system configured to identify a transition between stages of the CMP operation is also provided.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: August 19, 2008
    Assignee: Lam Research Corporation
    Inventors: Ramesh Gopalan, Sridharan Srivatsan, Katgenhalli Y. Ramanujam, Tom Ni, Conan Chiang
  • Patent number: 7040952
    Abstract: A method for preventing de-lamination of semiconductor wafer film stacks during a linear belt-type chemical mechanical planarization (CMP) process is provided. The method implements a pulsed polishing head rotation during a CMP process to maintain a slurry distribution across the width of a belt pad. The slurry distribution is maintained in a manner that prevents de-lamination of a wafer film having weak adhesion characteristics. Thus, the pulsed polishing head rotation implemented by the method reduces de-lamination of low-K material film layers during the CMP process.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 9, 2006
    Assignee: Lam Research Corporation
    Inventors: Sridharan Srivatsan, Ramesh Gopalan, K. Y. Ramanujam
  • Patent number: 6896586
    Abstract: A temperature controlling system for use in a chemical mechanical planarization (CMP) system having a linear polishing belt, a carrier capable of applying a substrate over a preparation location over the linear polishing belt is provided. The temperature controlling system includes a platen having a plurality of zones. The temperature controlling system further includes a temperature sensor configured determine a temperature of the linear polishing belt at a location that is after the preparation location. The system also includes a controller for adjusting a flow of temperature conditioned fluid to selected zones of the plurality of zones of the platen in response to output received from the temperature sensor.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: May 24, 2005
    Assignee: Lam Research Corporation
    Inventors: Xuyen Pham, Tuan Nguyen, Ren Zhou, David Wei, Linda Jiang, Katgenhalli Y. Ramanujam, Joseph P. Simon, Tony Luong, Sridharan Srivatsan, Anjun Jerry Jin
  • Publication number: 20030186623
    Abstract: A temperature controlling system for use in a chemical mechanical planarization (CMP) system having a linear polishing belt, a carrier capable of applying a substrate over a preparation location over the linear polishing belt is provided. The temperature controlling system includes a platen having a plurality of zones. The temperature controlling system further includes a temperature sensor configured determine a temperature of the linear polishing belt at a location that is after the preparation location. The system also includes a controller for adjusting a flow of temperature conditioned fluid to selected zones of the plurality of zones of the platen in response to output received from the temperature sensor.
    Type: Application
    Filed: March 29, 2002
    Publication date: October 2, 2003
    Applicant: LAM Research Corp.
    Inventors: Xuyen Pham, Tuan Nguyen, Ren Zhou, David Wei, Linda Jiang, Katgenhalli Y. Ramanujam, Joseph P. Simon, Tony Luong, Sridharan Srivatsan, Anjun Jerry Jin
  • Publication number: 20030060145
    Abstract: A multi-step polishing system, and a process for polishing a workpiece using the system. The system includes one or more polishing stations. The workpiece is polished in the presence of an oxidizer-free medium, and subsequently, the workpiece is polished in the presence of an oxidizing medium. This polishing sequence extends the life of the polishing pads and provides for a more uniform polish.
    Type: Application
    Filed: August 23, 2001
    Publication date: March 27, 2003
    Inventors: Youlin J. Li, Stephen Jew, Sridharan Srivatsan, K.Y. Ramanujam
  • Publication number: 20020185467
    Abstract: An interlocking polishing belt apparatus is disclosed. The interlocking polishing belt apparatus includes an interlocking belt, which includes a plurality of studs each having an upper stud end and a lower stud end. In addition, the interlocking polishing belt apparatus includes a polishing belt that is in contact with the interlocking belt. The polishing belt has a plurality of polishing belt stud holes, each configured to interlock with an upper stud end.
    Type: Application
    Filed: July 23, 2002
    Publication date: December 12, 2002
    Applicant: Lam Research Corporation
    Inventors: John Boyd, K. Y. Ramanujam, Sridharan Srivatsan, Xuyen Pham
  • Patent number: 6475332
    Abstract: An interlocking polishing belt apparatus is disclosed. The interlocking polishing belt apparatus includes an interlocking belt, which includes a plurality of studs each having an upper stud end and a lower stud end. In addition, the interlocking polishing belt apparatus includes a polishing belt that is in contact with the interlocking belt. The polishing belt has a plurality of polishing belt stud holes, each configured to interlock with an upper stud end.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: November 5, 2002
    Assignee: Lam Research Corporation
    Inventors: John Boyd, Katgenahalli Y. Ramanujam, Sridharan Srivatsan, Xuyen Pham