Abstract: Dynamic load balancing techniques among ports of a network device are provided. At a device configured to forward packets in a network, a plurality of queues are generated, each associated with a corresponding one of a plurality of output ports of the device and from which packets are to be output from the device into the network. When the number of packets in the at least one queue exceeds a threshold, for new packets that are to be enqueued to the at least one queue, packets are enqueued to a plurality of sub-queues such that packets are assigned to different ones of the plurality of sub-queues. Each of the plurality of sub-queues is associated with a corresponding one of the plurality of output ports. Packets of the plurality of sub-queues are output from corresponding ones of the plurality of output ports.

Abstract: A packet scheduler is configured to perform quality of service (QoS) scheduling on a per-data unit basis. A downstream processing engine is operatively connected to the packet scheduler for receiving forwarded packets. A feedback path is operatively connected between the downstream processing engine and the packet scheduler for transmitting a net data unit change value reflecting a change in packet size between an output of the packet scheduler and an output of the downstream processing engine.

Abstract: A packet scheduler is configured to perform quality of service (QoS) scheduling on a per-data unit basis. A downstream processing engine is operatively connected to the packet scheduler for receiving forwarded packets. A feedback path is operatively connected between the downstream processing engine and the packet scheduler for transmitting a net data unit change value reflecting a change in packet size between an output of the packet scheduler and an output of the downstream processing engine.

Abstract: A packet scheduler is configured to perform quality of service (QoS) scheduling on a per-data unit basis. A downstream processing engine is operatively connected to the packet scheduler for receiving forwarded packets. A feedback path is operatively connected between the downstream processing engine and the packet scheduler for transmitting a net data unit change value reflecting a change in packet size between an output of the packet scheduler and an output of the downstream processing engine.

Abstract: An integrated logic circuit according to the present invention includes a plurality of logic circuit elements, such as field effect transistors, for performing a combinational logic function, and at least one test controlled-impedance element for loading the logic circuit and causing a first digital output signal to be produced when the impedance of a logic circuit element under test is within a predetermined range and produce another digital output signal when the impedance of the logic circuit element under test is outside the predetermined range. The test controlled-impedance elements typically comprise field effect transistors and are sized in accordance with a series of constraints. The constraints are obtained by considering the operation of the circuit under various impedance fault conditions (high, low and intermediate) and deriving a series of size relationships between the impedance values of the logic circuit and test elements.