Patents by Inventor Srihari Vegesna
Srihari Vegesna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9100323Abstract: In general, the invention is directed to techniques for reducing deadlocks that may arise when performing fabric replication. For example, as described herein, a network device includes packet replicators that each comprises a plurality of resource partitions. A replication data structure for a packet received by the network device includes packet replicator nodes that are arranged hierarchically to occupy one or more levels of the replication data structure. Each of the resource partitions in each of the plurality of packet replicators is associated with a different level of the replication data structure. The packet replicators replicate the packet according to the replication data structure, and each of the packet replicators handles the packet using the one of the resource partitions of the packet replicator that is associated with the level of the replication data structure occupied by the node that corresponds to that particular packet replicator.Type: GrantFiled: December 9, 2013Date of Patent: August 4, 2015Assignee: Juniper Networks, Inc.Inventors: Pradeep Sindhu, Jean-Marc Frailong, Sarin Thomas, Srihari Vegesna, David J. Ofelt, Chang-Hong Wu
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Patent number: 9077466Abstract: In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.Type: GrantFiled: December 3, 2012Date of Patent: July 7, 2015Assignee: Juniper Networks, Inc.Inventors: Sarin Thomas, Srihari Vegesna, Pradeep Sindhu, Chi-Chung Kenny Chen, Jean-Marc Frailong, David J. Ofelt, Philip A. Thomas, Chang-Hong Wu
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Patent number: 8953625Abstract: A scheduler in a network element may include a dequeuer to dequeue packets from a set of scheduling nodes using a deficit weighted round robin process, where the dequeuer is to determine whether a subset of the set of scheduling nodes is being backpressured. The dequeuer may set a root rich most negative credits (MNC) value, associated with a root node, to a root poor MNC value, associated with the root node, and set the root poor MNC value to zero, when the subset is not being backpressured, and may set the rich MNC value to a maximum of the root poor MNC value and a root backpressured rich MNC value, associated with the subset, and set the root poor MNC value to a root backpressured poor MNC value, associated with the subset, when the subset is being backpressured.Type: GrantFiled: April 30, 2013Date of Patent: February 10, 2015Assignee: Juniper Networks, Inc.Inventors: Gary Goldman, Srihari Vegesna
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Patent number: 8797877Abstract: In general, techniques are described for allocating virtual output queue (VOQ) buffer space to ingress forwarding units of a network device based on drain rates at which network packets are forwarded from VOQs of the ingress forwarding units. For example, a network device includes multiple ingress forwarding units that each forward network packets to an output queue of an egress forwarding unit. Ingress forwarding units each include a VOQ that corresponds to the output queue. The drain rate at any particular ingress forwarding unit corresponds to its share of bandwidth to the output queue, as determined by the egress forwarding unit. Each ingress forwarding unit configures its VOQ buffer size in proportion to its respective drain rate in order to provide an expected delay bandwidth buffering for the output queue of the egress forwarding unit.Type: GrantFiled: August 9, 2012Date of Patent: August 5, 2014Assignee: Juniper Networks, Inc.Inventors: Srinivas Perla, Sanjeev Kumar, Avanindra Godbole, Srihari Vegesna, Sarin Thomas, Mahesh Dorai
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Patent number: 8605722Abstract: In general, the invention is directed to techniques for reducing deadlocks that may arise when performing fabric replication. For example, as described herein, a network device includes packet replicators that each comprises a plurality of resource partitions. A replication data structure for a packet received by the network device includes packet replicator nodes that are arranged hierarchically to occupy one or more levels of the replication data structure. Each of the resource partitions in each of the plurality of packet replicators is associated with a different level of the replication data structure. The packet replicators replicate the packet according to the replication data structure, and each of the packet replicators handles the packet using the one of the resource partitions of the packet replicator that is associated with the level of the replication data structure occupied by the node that corresponds to that particular packet replicator.Type: GrantFiled: April 14, 2010Date of Patent: December 10, 2013Assignee: Juniper Networks, Inc.Inventors: Pradeep Sindhu, Jean-Marc Frailong, Sarin Thomas, Srihari Vegesna, David J. Ofelt, Chang-Hong Wu
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Publication number: 20130235880Abstract: A scheduler in a network element may include a dequeuer to dequeue packets from a set of scheduling nodes using a deficit weighted round robin process, where the dequeuer is to determine whether a subset of the set of scheduling nodes is being backpressured. The dequeuer may set a root rich most negative credits (MNC) value, associated with a root node, to a root poor MNC value, associated with the root node, and set the root poor MNC value to zero, when the subset is not being backpressured, and may set the rich MNC value to a maximum of the root poor MNC value and a root backpressured rich MNC value, associated with the subset, and set the root poor MNC value to a root backpressured poor MNC value, associated with the subset, when the subset is being backpressured.Type: ApplicationFiled: April 30, 2013Publication date: September 12, 2013Applicant: JUNIPER NETWORKS, INC.Inventors: Gary GOLDMAN, Srihari Vegesna
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Patent number: 8522111Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.Type: GrantFiled: November 16, 2012Date of Patent: August 27, 2013Assignee: Juniper Networks, Inc.Inventors: Pradeep Sindhu, Srihari Vegesna
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Patent number: 8509069Abstract: A method includes receiving packets from a network with a plurality of packet-forwarding engines (PFEs) of a router, wherein the plurality of PFEs are interconnected by a switch fabric, determining an egress one of the PFEs for each of the packets, and forming fixed-sized fabric cells that share data associated with the packets that are destined for the same egress PFE while preventing packets destined for different egress PFEs to share any of the fabric cells. The fabric cells are transmitted through the switch fabric to communicate the packets to the egress PFEs.Type: GrantFiled: April 5, 2010Date of Patent: August 13, 2013Assignee: Juniper Networks, Inc.Inventors: Wing Leong Poon, Venkatraman Chandrasekaran, Srihari Vegesna, Sarin Thomas, David J. Ofelt
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Patent number: 8457142Abstract: A scheduler in a network element may include a dequeuer to dequeue packets from a set of scheduling nodes using a deficit weighted round robin process, where the dequeuer is to determine whether a subset of the set of scheduling nodes is being backpressured. The dequeuer may set a root rich most negative credits (MNC) value, associated with a root node, to a root poor MNC value, associated with the root node, and set the root poor MNC value to zero, when the subset is not being backpressured, and may set the rich MNC value to a maximum of the root poor MNC value and a root backpressured rich MNC value, associated with the subset, and set the root poor MNC value to a root backpressured poor MNC value, associated with the subset, when the subset is being backpressured.Type: GrantFiled: February 18, 2011Date of Patent: June 4, 2013Assignee: Juniper Networks, Inc.Inventors: Gary Goldman, Srihari Vegesna
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Patent number: 8363668Abstract: A network device includes multiple queues to store packets to be scheduled, and a weighted round-robin (WRR) scheduler. The WRR scheduler performs a first WRR scheduling iteration including processing of at least one packet from a particular queue of the multiple queues, identifies the particular queue as an empty queue during the performing of the first WRR scheduling iteration, identifies the particular queue as a non-empty queue after the identifying the particular queue as the empty queue, and performs a second WRR scheduling iteration including processing of only one packet of a group of packets from the particular queue of the multiple queues.Type: GrantFiled: December 17, 2009Date of Patent: January 29, 2013Assignee: Juniper Networks, Inc.Inventors: Sarin Thomas, Srihari Vegesna
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Patent number: 8325749Abstract: In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.Type: GrantFiled: December 24, 2008Date of Patent: December 4, 2012Assignee: Juniper Networks, Inc.Inventors: Sarin Thomas, Srihari Vegesna, Pradeep Sindhu, Chi-Chung Kenny Chen, Jean-Marc Frailong, David J. Ofelt, Philip A. Thomas, Chang-Hong Wu
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Patent number: 8321753Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.Type: GrantFiled: April 13, 2010Date of Patent: November 27, 2012Assignee: Juniper Networks, Inc.Inventors: Pradeep Sindhu, Srihari Vegesna
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Patent number: 8230110Abstract: In general, techniques are described for performing work conserving packet scheduling in network devices. For example, a network device comprising queues that store packets and a control unit may implement these techniques. The control unit stores data defining hierarchically-ordered nodes, which include leaf nodes from which one or more of the queues depend. The control unit executes first and second dequeue operations concurrently to traverse the hierarchically-ordered nodes and schedule processing of packets stored to the queues. During execution, the first dequeue operation masks at least one of the selected ones of the leaf nodes from which one of the queues depends based on scheduling data stored by the control unit. The scheduling data indicates valid child node counts in some instances. The masking occurs to exclude the node from consideration by the second dequeue operation concurrently executing with the first dequeue operation, which may preserve work in certain instances.Type: GrantFiled: July 13, 2010Date of Patent: July 24, 2012Assignee: Juniper Networks, Inc.Inventors: Srihari Vegesna, Sarin Thomas
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Publication number: 20110252284Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.Type: ApplicationFiled: April 13, 2010Publication date: October 13, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Pradeep SINDHU, Srihari Vegesna
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Publication number: 20110216773Abstract: In general, techniques are described for performing work conserving packet scheduling in network devices. For example, a network device comprising queues that store packets and a control unit may implement these techniques. The control unit stores data defining hierarchically-ordered nodes, which include leaf nodes from which one or more of the queues depend. The control unit executes first and second dequeue operations concurrently to traverse the hierarchically-ordered nodes and schedule processing of packets stored to the queues. During execution, the first dequeue operation masks at least one of the selected ones of the leaf nodes from which one of the queues depends based on scheduling data stored by the control unit. The scheduling data indicates valid child node counts in some instances. The masking occurs to exclude the node from consideration by the second dequeue operation concurrently executing with the first dequeue operation, which may preserve work in certain instances.Type: ApplicationFiled: July 13, 2010Publication date: September 8, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Srihari Vegesna, Sarin Thomas
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Publication number: 20110149977Abstract: A network device includes multiple queues to store packets to be scheduled, and a weighted round-robin (WRR) scheduler. The WRR scheduler performs a first WRR scheduling iteration including processing of at least one packet from a particular queue of the multiple queues, identifies the particular queue as an empty queue during the performing of the first WRR scheduling iteration, identifies the particular queue as a non-empty queue after the identifying the particular queue as the empty queue, and performs a second WRR scheduling iteration including processing of only one packet of a group of packets from the particular queue of the multiple queues.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Sarin THOMAS, Srihari VEGESNA
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Patent number: 7747915Abstract: A system and method for increasing the yield of integrated circuits containing memory partitions the memory into regions and then independently tests each region to determine which, if any, of the memory regions contain one or more memory failures. The test results are stored for later retrieval. Prior to using the memory, software retrieves the test results and uses only the memory sections that contain no memory failures. A consequence of this approach is that integrated circuits containing memory that would have been discarded for containing memory failures now may be used. This approach also does not significantly impact die area.Type: GrantFiled: January 5, 2009Date of Patent: June 29, 2010Assignee: NVIDIA CorporationInventors: Anthony M. Tamasi, Oren Rubenstein, Srihari Vegesna, Jue Wu, Sean J. Treichler
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Publication number: 20100158031Abstract: In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.Type: ApplicationFiled: December 24, 2008Publication date: June 24, 2010Inventors: Sarin Thomas, Srihari Vegesna, Pradeep Sindhu, Chi-Chung Kenny Chen, Jean-Marc Frailong, David J. Ofelt, Philip A. Thomas, Chang-Hong Wu
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Publication number: 20090164841Abstract: A system and method for increasing the yield of integrated circuits containing memory partitions the memory into regions and then independently tests each region to determine which, if any, of the memory regions contain one or more memory failures. The test results are stored for later retrieval. Prior to using the memory, software retrieves the test results and uses only the memory sections that contain no memory failures. A consequence of this approach is that integrated circuits containing memory that would have been discarded for containing memory failures now may be used. This approach also does not significantly impact die area.Type: ApplicationFiled: January 5, 2009Publication date: June 25, 2009Inventors: Anthony M. Tamasi, Oren Rubinstein, Srihari Vegesna, Jue Wu, Sean J. Treichler
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Patent number: 7478289Abstract: A system and method for increasing the yield of integrated circuits containing memory partitions the memory into regions and then independently tests each region to determine which, if any, of the memory regions contain one or more memory failures. The test results are stored for later retrieval. Prior to using the memory, software retrieves the test results and uses only the memory sections that contain no memory failures. A consequence of this approach is that integrated circuits containing memory that would have been discarded for containing memory failures now may be used. This approach also does not significantly impact die area.Type: GrantFiled: June 3, 2005Date of Patent: January 13, 2009Assignee: NVIDIA CorporationInventors: Anthony M. Tamasi, Oren Rubenstein, Srihari Vegesna, Jue Wu, Sean J. Treichler