Patents by Inventor Srijib Narayan

Srijib Narayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for multi-processor FFT/IFFT with minimum inter-processor data communication
    Patent number: 7870177
    Abstract: The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: January 11, 2011
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Kaushik Saha, Srijib Narayan
  • Method and system for multi-processor FFT/IFFT with minimum inter-processor data communication
    Patent number: 7739322
    Abstract: The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: June 15, 2010
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Kaushik Saha, Srijib Narayan
  • Method and system for multi-processor FFT/IFFT with minimum inter-processor data communication
    Publication number: 20040236809
    Abstract: The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
    Type: Application
    Filed: February 17, 2004
    Publication date: November 25, 2004
    Inventors: Kaushik Saha, Srijib Narayan