Patents by Inventor Srijib Narayan Maiti

Srijib Narayan Maiti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8705624
    Abstract: A method for decoding a stream encoded using a scalable video coding and including a plurality of layers of frames divided into a plurality of blocks, decodes block-wise in parallel the layers of the stream. A target block in an enhancement layer is decoded as soon as the block data required for its decoding are available from the reference layer.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: April 22, 2014
    Assignee: STMicroelectronics International N. V.
    Inventors: Amit Gupta, Srijib Narayan Maiti
  • Publication number: 20120287237
    Abstract: An embodiment of a method is disclosed for encoding a digital video signal including a first video sequence and a second video sequence jointly forming a stereo-view digital video signal. The method includes: subjecting the first video sequence to discrete cosine transform, quantization and run-length coding to produce a sequence of blocks of non-zero digital levels representative of the first video sequence, subjecting the second video sequence to discrete cosine transform, quantization, run-length coding and variable length coding to produce digital messages representative of the second video sequence, merging the bits of the digital messages into the sequence of blocks of digital levels by substituting the bits of the digital messages for respective Least Significant Bits of e.g. the last digital level in the blocks representative of the first video sequence to produce an encoded digital video signal representative of the first video sequence and the second video sequence.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 15, 2012
    Applicants: STMicroelectronics PVT LTD (INDIA), STMicroelectronics S.r.l.
    Inventors: Emiliano Mario PICCINELLI, Pasqualina FRAGNETO, Davide ALIPRANDI, Beatrice ROSSI, Srijib Narayan MAITI
  • Patent number: 7983342
    Abstract: A macro-block level parallel video decoder for a parallel processing environment is provided. The video decoder includes a Variable Length Decoding (VLD) block for decoding the encoded Discrete Cosine Transform (DCT) coefficients, a master node that receives the decoded DCT coefficients, and multiple slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at the macro-block level. Also provided is a method for macro-block level video decoding in a parallel processing system.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: July 19, 2011
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Kaushik Saha, Abhik Sarkar, Srijib Narayan Maiti
  • Publication number: 20110122944
    Abstract: A method for decoding a stream encoded using a scalable video coding and including a plurality of layers of frames divided into a plurality of blocks, decodes block-wise in parallel the layers of the stream. A target block in an enhancement layer is decoded as soon as the block data required for its decoding are available from the reference layer.
    Type: Application
    Filed: November 24, 2009
    Publication date: May 26, 2011
    Applicant: STMICROELECTRONICS Pvt. Ltd.
    Inventors: Amit GUPTA, Srijib Narayan MAITI
  • Patent number: 7774397
    Abstract: An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 10, 2010
    Assignee: STMicroelectronics (R&D) Ltd.
    Inventors: Kaushik Saha, Srijib Narayan Maiti, Marco Cornero
  • Publication number: 20040167950
    Abstract: A linear scalable method computes a Fast Fourier Transform (FFT) or Inverse Fast Fourier transform (IFFT) in a multiprocessing system using a decimation in time approach. Linear scalability means, as the number of processor increases by a factor P (for example), the computational cycle reduces by exactly the same factor P. The method includes computing the first two stages of an N-point FFT/IFFT as a single radix-4 butterfly computation operation while implementing the remaining (log2N−2) stages as radix-2 operations. Each radix-2 operation employs a single radix-2 butterfly computation loop without employing nested loops. The method also includes distributing the computation of the butterflies in each sage such that each processor computes an equal number of complete butterfly calculations thereby eliminating data interdependency in the stage.
    Type: Application
    Filed: December 3, 2003
    Publication date: August 26, 2004
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Kaushik Saha, Srijib Narayan Maiti