Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.

Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.