Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: Disclosed herein are memory devices with gradient-doped control gate material, as well as related methods and devices. In some embodiments, a memory device may include a first isolation material, a second isolation material, and a control gate material between the first isolation material and the second isolation material along an axis. The control gate material may include a dopant having a non-uniform concentration along the axis.

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract: A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.

Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.

Abstract: A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.