Abstract: A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.

Abstract: The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap.

Abstract: A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.

Abstract: A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.

Abstract: A semiconductor device and method of making the same forms a spacer by depositing a spacer layer over a substrate and a gate electrode and forms a protective layer on the spacer layer. The protective layer is dry etched to leave a thin film sidewall on the spacer layer. The spacer layer is then etched, with the protective layer protecting the outer sidewalls of the spacer layer. This etching creates spacers on the gate that have substantially vertical sidewalls that extend parallel to the gate electrode sidewalls. The I-shape of the spacers prevent punch-through during the source/drain ion implantation process, providing an improved source/drain implant dose profile.

Abstract: According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.

Abstract: A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.

Abstract: The method performs a first photolithography and etch to form shallow trench isolation features and alignment mark features into the top SOI layer. The shallow trenches are then filled with a dielectric material to form the isolation. A second lithography and etch step is then applied to etch the window locations for back-side contacts, and to transfer the alignment marks down into the SOI lower substrate. After this first lithography and etch step, the alignment marks in the top silicon may be used for alignment of the second lithography mask and etch. This is made possible by leaving the polish stop layer on the wafer, which serves to increase the optically effective thickness of the alignment mark pattern. The polish stop layer is removed after the second etch process. The teachings can be applied to any Semiconductor-On-Insulator-type wafer/technology where the top semiconductor layer is not thicker than the optimum alignment mark depth.

Abstract: A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.

Abstract: STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 ?. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.

Abstract: A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.

Abstract: A semiconductor device and method of making the same forms a spacer by depositing a spacer layer over a substrate and a gate electrode and forms a protective layer on the spacer layer. The protective layer is dry etched to leave a thin film sidewall on the spacer layer. The spacer layer is then etched, with the protective layer protecting the outer sidewalls of the spacer layer. This etching creates spacers on the gate that have substantially vertical sidewalls that extend parallel to the gate electrode sidewalls. The I-shape of the spacers prevent punch-through during the source/drain ion implantation process, providing an improved source/drain implant dose profile.

Abstract: A method for forming semiconductor features, e.g., gates, line widths, thicknesses and spaces, produced by a photoresist trim procedure, in a closed loop process is presented. The methodology enables the use of optical emission spectroscopy and/or optical interferometry techniques for endpoint monitoring during resist trim etching of photoresist structures. Various types of material layers underlying photoresist structures are employed in order to provide an endpoint signal to enable closed loop control, with resultant improved targeting of photoresist mask and reproducibility. In addition, the method provides for in situ etch rate monitoring, and is not adversely affected by etch rate variances within an etching chamber during an etch process.

Abstract: A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.

Abstract: A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.

Abstract: A method of producing an integrated circuit eliminates the need to re-oxidize polysilicon gate conductors and lines prior to removal of a hard mask used to form the gate conductors. A layer of polysilicon is provided above a semiconductor substrate. The layer of polysilicon is then doped. A mask material comprising amorphous carbon is provided above the layer of polysilicon, and the layer of mask material is patterned to form a mask. A portion of the layer of polysilicon is removed according to the mask, and the mask is removed.

Abstract: A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region is formed intermediate the amorphous carbon material layer and the ARC material layer. The transition region has a concentration profile that provides a transition between the amorphous carbon material layer and the ARC material layer. A portion of the amorphous carbon material layer, the ARC material layer, and the transition region is removed to form a hard mask, and a feature is formed in the layer of conductive material according to the hard mask.

Abstract: A method of forming a gate electrode for a fin field effect transistor (FinFET) includes forming a fin on a substrate and forming an oxide layer over the fin. The method further includes forming a carbon layer over the oxide layer and forming a trench in the oxide layer and the carbon layer, where the trench crosses over the fin. The method also includes filling the trench with a material to form the gate electrode.

Abstract: A method of forming a gate electrode for a fin field effect transistor (FinFET) is provided. The method includes forming a fin on a substrate and forming an oxide layer over the fin. The method further includes forming a trench in the oxide layer, the trench crossing over the fin, and filling the trench with a material to form a gate electrode.

Abstract: An exemplary embodiment relates to a method of using an amorphous carbon layer to prevent photoresist poisoning. The method includes doping a first amorphous carbon layer located above a substrate, providing an oxide layer above the first amorphous carbon layer where the oxide layer has a pinhole, and providing a second amorphous carbon layer adjacent to the oxide layer. The second amorphous carbon layer is undoped and the second amorphous carbon layer helps prevent photoresist poisoning.