Patents by Inventor Srikanth Balasubramanian
Srikanth Balasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11698671Abstract: Some aspects of this disclosure relate to a peak power manager that includes a first power estimate accumulator circuit configured to receive one or more power estimates associated with one or more subsystems and to generate a first accumulated power estimate. The peak power manage can further include a first-in first-out (FIFO) storage circuit configured to store a plurality of first accumulated power estimates associated with a plurality of clock cycles corresponding to a moving time interval window. The peak power manager can further include a second power estimate accumulator circuit configured to accumulate the plurality of first accumulated power estimates to generate a second accumulated power estimate and a control circuit.Type: GrantFiled: September 22, 2021Date of Patent: July 11, 2023Assignee: Apple Inc.Inventors: Preethi Bhargavi Sama, Richard H. Larson, Shih-Chieh Wen, Srikanth Balasubramanian
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Patent number: 11675409Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.Type: GrantFiled: July 12, 2022Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Matthias Knoth, Srikanth Balasubramanian, Venkatram Krishnaswamy, Ramesh B. Gunna
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Publication number: 20230092988Abstract: Some aspects of this disclosure relate to a peak power manager that includes a first power estimate accumulator circuit configured to receive one or more power estimates associated with one or more subsystems and to generate a first accumulated power estimate. The peak power manage can further include a first-in first-out (FIFO) storage circuit configured to store a plurality of first accumulated power estimates associated with a plurality of clock cycles corresponding to a moving time interval window. The peak power manager can further include a second power estimate accumulator circuit configured to accumulate the plurality of first accumulated power estimates to generate a second accumulated power estimate and a control circuit.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: Apple Inc.Inventors: Preethi Bhargavi SAMA, Richard H. LARSON, Shih-Chieh WEN, Srikanth BALASUBRAMANIAN
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Publication number: 20220342471Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.Type: ApplicationFiled: July 12, 2022Publication date: October 27, 2022Inventors: Matthias Knoth, Srikanth Balasubramanian, Venkatram Krishnaswamy, Ramesh B. Gunna
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Patent number: 11429555Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.Type: GrantFiled: February 26, 2019Date of Patent: August 30, 2022Assignee: Apple Inc.Inventors: Aditya Kesiraju, Andrew J. Beaumont-Smith, Boris S. Alvarez-Heredia, Srikanth Balasubramanian
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Patent number: 11416056Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.Type: GrantFiled: September 18, 2020Date of Patent: August 16, 2022Assignee: Apple Inc.Inventors: Matthias Knoth, Srikanth Balasubramanian, Venkatram Krishnaswamy, Ramesh B. Gunna
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Patent number: 11347198Abstract: Systems, apparatuses, and methods for implementing an optimized adaptive thermal control mechanism for an integrated circuit (IC) are described. A control unit receives a digital input value which is representative of a temperature of an IC. The control unit compares the input value to at least two set points. A result of a first comparison determines whether an accumulator is incremented or decremented by a programmable gain value. A result of a second comparison determines whether the accumulator is primed with a preset ramp-up value. The preset ramp-up value is used since the accumulator can take several sensing cycles to reach the optimal control value while thermal gradients can become critical in only a few cycles. The output of the accumulator is provided to an actuator which adjusts parameter(s) to modulate the IC's temperature. The granularity and range of the accumulator matches the granularity and range of the actuator.Type: GrantFiled: September 4, 2020Date of Patent: May 31, 2022Assignee: Apple Inc.Inventors: Matthias Knoth, Ramesh B. Gunna, Srikanth Balasubramanian
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Publication number: 20220091649Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Matthias Knoth, Srikanth Balasubramanian, Venkatram Krishnaswamy, Ramesh B. Gunna
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Publication number: 20220075343Abstract: Systems, apparatuses, and methods for implementing an optimized adaptive thermal control mechanism for an integrated circuit (IC) are described. A control unit receives a digital input value which is representative of a temperature of an IC. The control unit compares the input value to at least two set points. A result of a first comparison determines whether an accumulator is incremented or decremented by a programmable gain value. A result of a second comparison determines whether the accumulator is primed with a preset ramp-up value. The preset ramp-up value is used since the accumulator can take several sensing cycles to reach the optimal control value while thermal gradients can become critical in only a few cycles. The output of the accumulator is provided to an actuator which adjusts parameter(s) to modulate the IC's temperature. The granularity and range of the accumulator matches the granularity and range of the actuator.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Matthias Knoth, Ramesh B. Gunna, Srikanth Balasubramanian
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Patent number: 11138857Abstract: Described here is a portable sensor for detecting a loss of balance consisting of an accelerometer, a gyroscope, an alerting signal module and a smart device in communication with a microcontroller. Also described is a wearable postural sensor for protecting a user from a fall-related injury consisting of a microcontroller, an integrated motion processing module, an alerting signal module, a smart device and an optional safety device such as an air bag. Also described is a method for preventing a fall and a fall-related injury by monitoring realtime changes in the rotation angle, planar rotation or sway velocity of the postural sensor.Type: GrantFiled: September 30, 2019Date of Patent: October 5, 2021Inventors: Siddharth Krishnakumar, Srikanth Balasubramanian
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Patent number: 10969858Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.Type: GrantFiled: January 3, 2019Date of Patent: April 6, 2021Assignee: Apple Inc.Inventors: Daniel U. Becker, Aditya Kesiraju, Srikanth Balasubramanian, Venkatram Krishnaswamy, Boris S. Alvarez-Heredia
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Publication number: 20210097840Abstract: Described here is a portable sensor for detecting a loss of balance consisting of an accelerometer, a gyroscope, an alerting signal module and a smart device in communication with a microcontroller. Also described is a wearable postural sensor for protecting a user from a fall-related injury consisting of a microcontroller, an integrated motion processing module, an alerting signal module, a smart device and an optional safety device such as an air bag. Also described is a method for preventing a fall and a fall-related injury by monitoring realtime changes in the rotation angle, planar rotation or sway velocity of the postural sensor.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: Siddharth Krishnakumar, Srikanth Balasubramanian
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Publication number: 20200272597Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.Type: ApplicationFiled: February 26, 2019Publication date: August 27, 2020Inventors: Aditya Kesiraju, Andrew J. Beaumont-Smith, Boris S. Alvarez-Heredia, Pradeep Kanapathipillai, Ran A. Chachick, Srikanth Balasubramanian
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Publication number: 20200218327Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.Type: ApplicationFiled: January 3, 2019Publication date: July 9, 2020Inventors: Daniel U. Becker, Aditya Kesiraju, Srikanth Balasubramanian, Venkatram Krishnaswamy, Boris S. Alvarez-Heredia
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Patent number: 9405358Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.Type: GrantFiled: October 16, 2014Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Srikanth Balasubramanian, Tessil Thomas, Satish Shrimali, Baskaran Ganesan
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Patent number: 9335803Abstract: In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.Type: GrantFiled: February 15, 2013Date of Patent: May 10, 2016Assignee: Intel CorporationInventors: Zhiguo Wang, David J. Ayers, Srikanth Balasubramanian, Sukirti Gupta, Stefan Rusu, Stephen M. Ramey
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Publication number: 20150039920Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.Type: ApplicationFiled: October 16, 2014Publication date: February 5, 2015Inventors: SRIKANTH BALASUBRAMANIAN, TESSIL THOMAS, SATISH SHRIMALI, BASKARAN GANESAN
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Patent number: 8892929Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.Type: GrantFiled: February 28, 2013Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Srikanth Balasubramanian, Tessil Thomas, Satish Shrimali, Baskaran Ganesan
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Patent number: 8892924Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.Type: GrantFiled: May 31, 2011Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Srikanth Balasubramanian, Tessil Thomas, Satish Shrimali, Baskaran Ganesan
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Publication number: 20140237267Abstract: In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Inventors: Zhiguo Wang, David J. Ayers, Srikanth Balasubramanian, Sukirti Gupta, Stefan Rusu, Stephen M. Ramey