Patents by Inventor Srikanth Bojja
Srikanth Bojja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10254783Abstract: A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.Type: GrantFiled: August 31, 2017Date of Patent: April 9, 2019Assignee: Western Digital Technologies, Inc.Inventors: Nitin Gupta, Bhavin Odedara, Raghu Voleti, Srikanth Bojja
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Publication number: 20190004562Abstract: A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.Type: ApplicationFiled: August 31, 2017Publication date: January 3, 2019Inventors: Nitin Gupta, Bhavin Odedara, Raghu Voleti, Srikanth Bojja
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Patent number: 9886080Abstract: A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.Type: GrantFiled: April 28, 2015Date of Patent: February 6, 2018Assignee: SanDisk Technologies LLCInventors: Anil Kumar Thadi Suryaprakash, Krishnamurthy Dhakshinamurthy, Ajay Dhingra, Rampraveen Somasundaram, Narendhiran Chinnaanangur Ravimohan, Bhavin Odedara, Srikanth Bojja, Jayanth Thimmaiah
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Publication number: 20180026646Abstract: A phase-locked loop (PLL) circuit may be configured to generate a plurality of oscillating signals based on a single control voltage generated based on a phase difference between an input signal and a feedback signal. One of the plurality of oscillating signals may be used to generate the feedback signal.Type: ApplicationFiled: July 25, 2016Publication date: January 25, 2018Applicant: SanDisk Technologies LLCInventors: Bhavin Odedara, Srikanth Bojja, Jayanth Mysore Thimmaiah, Srinivasa Rao Sabbineni
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Patent number: 8856712Abstract: A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.Type: GrantFiled: October 24, 2012Date of Patent: October 7, 2014Assignee: SanDisk Technologies Inc.Inventors: Deepak Pancholi, Srikanth Bojja, Bhavin Odedara
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Patent number: 8669817Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: GrantFiled: November 21, 2011Date of Patent: March 11, 2014Assignee: SanDisk Technologies Inc.Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi
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Publication number: 20140043078Abstract: A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.Type: ApplicationFiled: October 24, 2012Publication date: February 13, 2014Applicant: SanDisk Technologies Inc.Inventors: Deepak Pancholi, Srikanth Bojja, Bhavin Odedara
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Publication number: 20120062326Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi
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Patent number: 8085099Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: GrantFiled: April 6, 2010Date of Patent: December 27, 2011Assignee: SanDisk Technologies Inc.Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi
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Publication number: 20110241784Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.Type: ApplicationFiled: April 6, 2010Publication date: October 6, 2011Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi