Abstract: Embodiments of the present disclosure include techniques for encoding and decoding metadata in error correction codes. During read operation, a decoder generates a first output corresponding to the at least one metadata bit having a first state and a second output corresponding to the at least one metadata bit having a second state. When one of the first and second outputs have a zero value, the decoder sets a value of the at least one metadata bit to the first state or the second state corresponding to the first output or the second output having the zero value. When both the first and second outputs are non-zero, the decoder decodes the codeword with the assumption of both the metadata bit having the first state and the second state to determine if the codeword is correctable with the at least one metadata bit.

Abstract: Embodiments generally relate to improving reliability of processing cache lines with metadata symbols encoded into parity symbols of codewords. The data and metadata of a cache line are encoded into codewords where each codeword is a number of (1) message symbols, each including message bits from data of the cache line, and (2) parity symbols, each including parity bits determined from the message symbols and a metadata symbol. For each codeword of the cache line, the plurality of message and parity symbols are rotated so that a location of each symbol of one codeword is different from other codewords of the cache line. The codewords of the cache line are then stored in memory as rotated. In this manner, the reliability is improved by rotating symbols of the codewords of the cache line, with metadata symbols encoded into parity of codewords, before storage in memory.

Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.