Abstract: A method comprises performing a first pass test over a plurality of sets of equalization coefficients to filter the plurality of sets of equalization coefficients to produce one or more filtered sets of equalization coefficients. Each filtered set of equalization coefficients meets a first predetermined threshold. The method also comprises performing a second pass test over the one or more filtered sets of equalization coefficients to determine a final set of equalization coefficients that meets a second predetermined threshold. The second pass test produces more accurate results than the first pass test.

Abstract: A method comprises performing a first pass test over a plurality of sets of equalization coefficients to filter the plurality of sets of equalization coefficients to produce one or more filtered sets of equalization coefficients. Each filtered set of equalization coefficients meets a first predetermined threshold. The method also comprises performing a second pass test over the one or more filtered sets of equalization coefficients to determine a final set of equalization coefficients that meets a second predetermined threshold. The second pass test produces more accurate results than the first pass test.

Abstract: A dual data rate flip-flop circuit for reducing single event upset errors in the flip-flop circuit including two or more latch circuits connected in parallel. The latch circuits each have a clock input, data input, and latch circuit output. The dual data rate flip-flop circuit also includes a C-element, which has a plurality of inputs and a C-element output. The outputs of the latch circuits are provided to inputs of the C-element, and a keeper circuit is connected to the C-element output. An output buffer inverter connects to the C-element output and has an output corresponding to the dual data rate flip-flop circuit output.