Patents by Inventor Srikanth Jadcherla

Srikanth Jadcherla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240148266
    Abstract: The present inventions, in one aspect, are directed to bioimpedance sensing devices, systems, and methods, including, for example, utilizing a wearable sensing garment and/or accessory, that sense, acquire, detect and/or measure bioimpedance data to, in one embodiment, calculate, assess, determine and/or monitor data associated with, corresponding to and/or representative of a biological properties (e.g., fluid state or state of hydration) in an animal body (e.g., a human). The wearable sensing garment and/or accessory, having bioimpedance sensors thereon or therein, may be, for example, made of any material now known or later developed and preferably fits tight/snug (selectively or entirely) to the body of the animal so that the bioimpedance sensors make suitable contact to the body to facilitate acquisition of bioimpedance data (e.g., intermittent, periodic, continuous and/or substantially continuous data acquisition).
    Type: Application
    Filed: October 25, 2023
    Publication date: May 9, 2024
    Inventors: Michael H. Burnam, Srikanth Jadcherla
  • Patent number: 11213238
    Abstract: The various embodiments of the present invention disclose a stand-alone, scalable cardiac health monitoring device for 1-6-12 lead ECG data acquisition and a method of working thereof. The method of monitoring cardiac health condition of a patient comprises of receiving, by a cardiac monitoring device, an electrocardiograph (ECG) input data signals from at least two electrodes attached to the patient, performing, a quality check on acquiring the ECG input data signals, processing the acquired ECG input data signals, encrypting the processed ECG input data signals and transmitting the encrypted ECG signals to one or more external user devices over a wireless communication interface. The acquiring the ECG input data signals comprises of integrating a closed loop Right Leg Drive (RLD) as a shield drive and a cable/electrode shield to reduce noise coupling to the ECG input data signals.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: January 4, 2022
    Assignee: IMEDRIX SYSTEMS PRIVATE LIMITED
    Inventors: Rajaram Shastri, Nagesh Rangappan, Venkatakrishna Araveti, Niranjan Rayaprolu, Srikanth Jadcherla, Kishore Ramasamy, Lokesh Kumar Kata
  • Publication number: 20190290151
    Abstract: The various embodiments of the present invention disclose a stand-alone, scalable cardiac health monitoring device for 1-6-12 lead ECG data acquisition and a method of working thereof. The method of monitoring cardiac health condition of a patient comprises of receiving, by a cardiac monitoring device, an electrocardiograph (ECG) input data signals from at least two electrodes attached to the patient, performing, a quality check on acquiring the ECG input data signals, processing the acquired ECG input data signals, encrypting the processed ECG input data signals and transmitting the encrypted ECG signals to one or more external user devices over a wireless communication interface. The acquiring the ECG input data signals comprises of integrating a closed loop Right Leg Drive (RLD) as a shield drive and a cable/electrode shield to reduce noise coupling to the ECG input data signals.
    Type: Application
    Filed: December 31, 2017
    Publication date: September 26, 2019
    Inventors: Rajaram Shastri, Nagesh Rangappan, Venkatakrishna Araveti, Niranjan Rayaprolu, Srikanth Jadcherla, Kishore Ramasamy, Lokesh Kumar Kata
  • Publication number: 20130252223
    Abstract: The present invention relates to a system and method for enhancing innovative abilities by providing quality education and practical skills to the students and inculcating explorative and experimental learning skills in the students located at geographically apart locations comprising an administrative body 200, at least one adjustable classroom in at least one college or study centre 201, at least one interaction terminal 11, means for online interactive communication, means for offline communication, local server 40, at least one expert instructor 12, at least one student 100 at geographically apart location, at least one local coordinator 13, support means, forum for continuous support and assessment means. The method of instruction in the invention provides a more practical approach to learning the subject and prepares the students to effectively meet the technical skill requirements of the industry.
    Type: Application
    Filed: July 27, 2011
    Publication date: September 26, 2013
    Inventor: Srikanth Jadcherla
  • Patent number: 8255859
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: August 28, 2012
    Assignee: Synopsys, Inc.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • Patent number: 7984398
    Abstract: Systems and methods are disclosed herein which compensate for the loss in design information that occurs when the design is represented in traditional functional descriptions. An automated multiple voltage/power state design process includes creating a plurality of design objects; processing a design definition according to the voltage effects design object; and generating a modified design output such that communication between a plurality of design process steps, wherein the plurality of design process steps include a parsing step, a RTL simulation step, a synthesis step, a gate simulation step, formal verification step, and physical design and verification step in accordance with the voltage effects design object.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 19, 2011
    Assignee: Synopsys, Inc.
    Inventor: Srikanth Jadcherla
  • Patent number: 7694241
    Abstract: Automated design process and method with set of syntactic elements compensates for inability to represent voltage island connection of multi-rail cells in RTL source files in traditional design process which inhibits development of design automation methods and causes hardship and risk of failure to simulate, synthesize, perform physical design or formally verify a semiconductor chip design implemented with multi-rail.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: April 6, 2010
    Assignee: Synopsys, Inc.
    Inventors: Srikanth Jadcherla, Sriram Kotni
  • Patent number: 7694252
    Abstract: Verification of a design for a multi-voltage circuit which defines a plurality of iso-voltage rail blocks, and which comprises voltage state information for the iso-voltage-rail blocks. Verification includes generating cross-over information regarding a cross-over signal between two iso-voltage-rail blocks, identifying the voltage state relationship between the two iso-voltage-rail blocks based on the voltage state information, and verifying the validity of the cross-over signal based on the determined voltage state relationship.
    Type: Grant
    Filed: April 21, 2007
    Date of Patent: April 6, 2010
    Assignee: Synopsys, Inc.
    Inventors: Saptarshi Biswas, Srikanth Jadcherla, Sriram Kotni, Debabrata Bagchi
  • Publication number: 20090228852
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 10, 2009
    Applicant: SYNOPSYS, INC.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • Patent number: 7546566
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: June 9, 2009
    Assignee: Synopsys, Inc.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • Publication number: 20080250364
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 9, 2008
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • Patent number: 7340696
    Abstract: An automated design process and chip description system is disclosed. The automated design process and chip description system compensates for the loss in design information that occurs when the design is represented in traditional functional descriptions. The automated design process includes the steps of processing a design definition according to a functional description and generating a modified design output such that communication between design process steps is seamless. The chip description system comprises a storage element and a functional element, wherein a first design object couples to a second design object such that the coupling uses at least one functional element to access one or more storage elements usable by the chip description system.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: March 4, 2008
    Assignee: Archpro Design Automation, Inc.
    Inventor: Srikanth Jadcherla