Patents by Inventor Srikanth Jagannathan
Srikanth Jagannathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10734974Abstract: A circuit includes a transmitter circuit which includes a single-to-complementary circuit, a driver stage, and a pre-emphasis control circuit. The single-to-complementary circuit generates complementary output signals from a single ended input signal. The driver stage includes inputs to receive the complementary output signals, the driver stage includes a main driver circuit and a pre-emphasis driver circuit, and the pre-emphasis driver circuit is active during transitions of the complementary output signals to provide additional current for the driver stage. The pre-emphasis control circuit includes an RC pulse generation circuit in which the RC pulse generation circuit includes a capacitance and a resistance, and the RC pulse generation circuit provides, based on edges of a signal, pulses having a duration based on an RC time constant of the capacitance and resistance. The pre-emphasis driver circuit is active to provide additional current for the driver stage in response to the pulses.Type: GrantFiled: April 12, 2019Date of Patent: August 4, 2020Assignee: NXP USA, Inc.Inventors: Srikanth Jagannathan, Kumar Abhishek
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Publication number: 20200243122Abstract: A data processing system includes an SRAM array, wherein the plurality of SRAM cells provide a physically unclonable function (PUF). A PUF evaluation engine includes a selection circuit for selecting one or more word lines coupled to the plurality of SRAM cells in response to a challenge, and a cross-coupled latch coupled to two bit lines corresponding to two different SRAM cells of the plurality of SRAM cells. The cross-coupled latch is configured to provide one of two 2-bit values depending on which of the two bit lines discharges faster upon the two different SRAM cells being selected by the selection circuit, wherein the 2-bit value is part of a digital code provided in response to the challenge.Type: ApplicationFiled: January 29, 2019Publication date: July 30, 2020Inventors: NIHAAR N. MAHATME, SRIKANTH JAGANNATHAN
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Patent number: 10700691Abstract: A circuit includes a first external terminal, a first lower resolution analog-to-digital converter (LRADC) coupled to the external terminal and configured to perform a first conversion of an analog signal received at the external terminal to a digital value, and a higher resolution analog-to-digital converter (HRADC). The HRADC is configured to selectively receive the analog signal from the first external terminal based on the digital value. When the digital value outputted by the first LRADC indicates a change in value of the received analog signal, the HRADC is provided with the analog signal and performs a second conversion of the analog signal to a second digital value. The first LRADC has a lower conversion resolution as compared to the HRADC.Type: GrantFiled: May 30, 2019Date of Patent: June 30, 2020Assignee: NXP USA, INC.Inventors: Srikanth Jagannathan, Christopher James Micielli, George Rogers Kunnen, Carl Culshaw
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Publication number: 20200191862Abstract: An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.Type: ApplicationFiled: December 18, 2018Publication date: June 18, 2020Inventors: Kumar ABHISHEK, Srikanth JAGANNATHAN, Hector SANCHEZ
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Patent number: 10680594Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.Type: GrantFiled: July 10, 2018Date of Patent: June 9, 2020Assignee: NXP USA, Inc.Inventors: Christopher James Micielli, Srikanth Jagannathan, Manmohan Rana, Carl Culshaw
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Publication number: 20200136373Abstract: An integrated circuit includes a signal pad, an output buffer having an output coupled to the signal pad and having an enable input, an input buffer having an input coupled to the signal pad and having an enable input, a counter, and a gating circuit. The counter is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one. The gating circuit is configured to, in response to the counter expiring, disable the input buffer and the output buffer.Type: ApplicationFiled: October 25, 2018Publication date: April 30, 2020Inventors: KUMAR ABHISHEK, Srikanth Jagannathan
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Publication number: 20200021279Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.Type: ApplicationFiled: July 10, 2018Publication date: January 16, 2020Inventors: CHRISTOPHER JAMES MICIELLI, SRIKANTH JAGANNATHAN, MANMOHAN RANA, CARL CULSHAW
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Publication number: 20190288654Abstract: An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.Type: ApplicationFiled: March 14, 2018Publication date: September 19, 2019Inventors: KUMAR ABHISHEK, Srikanth Jagannathan
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Patent number: 10418952Abstract: An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.Type: GrantFiled: March 14, 2018Date of Patent: September 17, 2019Assignee: NXP USA, INC.Inventors: Kumar Abhishek, Srikanth Jagannathan
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Patent number: 10361732Abstract: An integrated circuit includes a transmitter having a data input coupled to receive a single-ended data signal, a reference input coupled to receive a bandgap reference, a first differential output, and a second differential output. The transmitter is configured to, during normal operation, convert the single-ended data signal at the data input into a first differential signal at the first differential output and a second differential signal at the second differential output in which the first differential signal and the second differential signal are complementary to each other. A fault detection circuit is coupled to the first and second differential outputs and is configured to detect a load short fault condition and a bandgap short condition based on the first and second differential signals at the first and second differential outputs while forcing the data input to zero.Type: GrantFiled: October 10, 2018Date of Patent: July 23, 2019Assignee: NXP USA, Inc.Inventors: Srikanth Jagannathan, Kumar Abhishek
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Patent number: 10312929Abstract: The embodiments described herein provide analog-to-digital converters and methods that can reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals while still providing the ability to perform an accurate analog-to-digital conversion. In general, the embodiments described herein reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals by pre-charging the sampling capacitor used in the conversion. For example, the embodiments can apply the buffered input signal apply to the sampling capacitor for a first sampling cycle to pre-charge the sampling capacitor, and then directly apply the unbuffered input signal to the sampling capacitor for a second sampling cycle to final-charge the sampling capacitor. With the sampling capacitor charged using the two stage charging, a digital output corresponding to the charge of the sampling capacitor is generated.Type: GrantFiled: June 4, 2018Date of Patent: June 4, 2019Assignee: NXP USA, Inc.Inventors: Kumar Abhishek, Srikanth Jagannathan, Shanaka Pradeep Yapa Appuhamillage Don
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Patent number: 10205441Abstract: A level shifter includes a level shifting circuit, a variable bias voltage generator, and a bias voltage generator controller. The level shifting circuit is configured to level shift an input signal at a first voltage level to an output signal having a second voltage level. The second voltage level is higher than the first voltage level. The level shifting circuit includes a current mirror, an input circuit for receiving the differential input signals, and a coupling circuit for coupling the current mirror to the input circuit in response to a variable bias voltage. The variable bias voltage generator is configured to provide the variable bias voltage at one of a plurality of voltage levels. The bias voltage generator controller provides a select signal to select the voltage level from the plurality of voltage levels in response to measuring the duty cycle of the output signal to maintain the duty cycle of the output signal at a predetermined duty cycle.Type: GrantFiled: December 14, 2017Date of Patent: February 12, 2019Assignee: NXP USA, Inc.Inventors: Kumar Abhishek, Srikanth Jagannathan
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Patent number: 10157087Abstract: A clock generator circuit includes an internal reference clock generator, a sequential circuit, and a pulse generator circuit. The internal reference clock generator circuit receives a clock buffer signal, a reset signal, and provides a first clock signal. The sequential circuit receives the first clock signal, and provides an internal reference clock signal based on the first clock signal. The pulse generator circuit receives the internal reference clock signal, a slow ring oscillator clock signal, and the reset signal. The pulse generator circuit counts a number of internal reference clock signals cycles for each cycle of the slow ring oscillator clock signal, and generates a pulse signal in response to the number being equal to zero during a cycle of the slow ring oscillator clock signal. The pulse signal toggles the flip-flop clock circuit to recover from a deadlock.Type: GrantFiled: July 14, 2017Date of Patent: December 18, 2018Assignee: NXP USA, Inc.Inventors: Kumar Abhishek, Srikanth Jagannathan
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Patent number: 10153768Abstract: Input/output circuitry includes a first PMOS device and a first NMOS device having first current electrodes are connected to each other and a pad. First selection circuitry, when the I/O circuitry is disabled, provides a first supply voltage to a control electrode and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltages and to directly provide the pad voltage to the control electrode and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage. Similarly, second selection circuitry, when the I/O circuitry is disabled, provides a second supply voltage or directly provides the pad voltage to a control electrode and a P-well of the first NMOS device depending on whether the pad voltage is between the first and second supply voltages or less than the second supply voltage, respectively.Type: GrantFiled: February 28, 2018Date of Patent: December 11, 2018Assignee: NXP USA, Inc.Inventors: Christopher James Micielli, Srikanth Jagannathan, Hector Sanchez, Kumar Abhishek
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Patent number: 10148261Abstract: A low voltage differential signaling (LVDS) driver circuit, system, apparatus, and methodology are provided for controlling switching components in a primary current stage and a pre-emphasis current stage with an adaptive pre-emphasis gain tuning hardware control circuit arranged to provide control signals for periodically tuning a pre-emphasis gain setting for the secondary pre-emphasis current stage by selecting an optimum pre-emphasis gain setting from a plurality of pre-emphasis gain setting which minimizes an inter-symbol interference (ISI) jitter measure for the LVDS driver circuit.Type: GrantFiled: December 18, 2017Date of Patent: December 4, 2018Assignee: NXP USA, Inc.Inventors: Srikanth Jagannathan, Kumar Abhishek
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Patent number: 10013042Abstract: A memory system includes a core power supply node configured to provide a core power supply; backup regulator configured to provide a backup power supply; memory configured to be powered by the core power supply or the backup power supply; threshold detection circuitry configured to provide a first indicator that when asserted indicates the core power supply has fallen to a first threshold, a second indicator that when asserted indicates the core power supply has fallen to a second threshold, and a third indicator that when asserted indicates the core power supply has fallen to a third threshold. The memory system also includes power sequence detection circuitry is configured to determine, upon the core power supply falling and based on which of the first, second, and third indicators are asserted, whether the asserted indicators have been asserted in a correct sequence and provide a first test result accordingly.Type: GrantFiled: July 20, 2017Date of Patent: July 3, 2018Assignee: NXP USA, Inc.Inventors: Kumar Abhishek, Srikanth Jagannathan
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Patent number: 9947391Abstract: A physically unclonable function (PUF) is implemented in a plurality of SRAM cells. In a method for generating a PUF response, a logic zero is first written to all the SRAM cells of the PUF. A bit line coupled to the storage node that stores the logic zero of each SRAM cell is biased to a predetermined voltage. The bit lines are then selected for an evaluation read operation. During the evaluation read, a read current of one of the bit lines from one column is converted to a first voltage and a read current of another bit line of another column is converted to a second voltage. The first voltage is then compared to the second voltage. A logic state of a bit of the PUF response is determined as a result of the comparison. The logic bit may be provided to the input of a parallel-in serial-out shift register. There may be a comparator for each logic bit, or a few comparators may be shared between the logic bits. The PUF response may be used to provide a signature for the data processing system.Type: GrantFiled: April 12, 2017Date of Patent: April 17, 2018Assignee: NXP USA, Inc.Inventors: Nihaar N. Mahatme, Srikanth Jagannathan, Alexander Hoefler
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Patent number: 9559671Abstract: A master slave storage circuit can include a first master portion coupled to a first master data storage node and a first slave portion coupled to a first slave data storage node. The first master portion can comprise one of a first master latch or a first master capacitive element coupled to the first master data storage node and the first slave portion comprises one of a first slave latch or a first slave capacitive element coupled to the first slave data storage node. If the first master portion comprises the first master latch, the first slave portion comprises the first slave capacitive element, and if the first master portion comprises the first master capacitive element, the first slave portion comprises the first slave latch.Type: GrantFiled: December 17, 2015Date of Patent: January 31, 2017Assignee: NXP USA, Inc.Inventors: Srikanth Jagannathan, Nihaar N. Mahatme, Kumar Abhishek