Patents by Inventor Srikanth Kulkarni
Srikanth Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143546Abstract: Disclosed examples include causing transmission of an indication to a server. The indication indicates that a file on a host storage location is designated as a favorite file. The indication causes a copy of the file to be stored in a favorites storage device. Disclosed examples also include generating a modified copy of the file by modifying the file at the host storage location, and causing synchronization of the modified copy of the file from the host storage location to replace the copy of the file at the favorites storage device.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Kranthikumar Gadde, Mitesh Kumar, Kamlesh Halder, Raj Vardhan, Srikanth Nalluri, Dattatraya Kulkarni, Susmita Nayak, Krishnapur Venkatasubrahmanyam
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Publication number: 20240137383Abstract: There is disclosed herein a computer-implemented system and method of providing wellness detect and response (WDR) security services for an enterprise, including computing, for the enterprise, a quantitative user-centric security posture, wherein computing the quantitative user-centric security posture comprises calculating, for a user, a quantitative user risk profile according to a combination of user role, user privileges, user behavior, and digital assets assigned to a user and owned by the enterprise.Type: ApplicationFiled: December 15, 2023Publication date: April 25, 2024Applicant: McAfee, LLCInventors: Dattatraya Kulkarni, Raghavendra Satyanarayana Hebbalalu, Srikanth Nalluri, Urmil Mahendra Parikh, Shashank Jain, Himanshu Srivastava, Piyush Pramod Joshi, Partha Sarathi Barik, Purushothaman Balamurugan, Saravana Kumar Ramalingam, Devanshi Saxena, Martin Pivetta, Sujay Subrahmanya, Shahmeet Singh, Ryan Burrows, Samrat Chitta
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Patent number: 11966787Abstract: There is disclosed in one example a computer apparatus, including: a hardware platform including a central processor unit (CPU) and a memory; and instructions encoded within the memory to instruct the CPU to: enumerate a plurality of running processes, and associate resource demands with the running processes; predict a resource starvation condition for at least one process; rank the plurality of running processes according to a dynamic ranking algorithm, wherein the ranking algorithm includes user engagement as an input for ranking a process; and according to the ranking and a safeguard algorithm, deallocate resources from a process ranked lower than the at least one process and assign the deallocated resources to the at least one process to mitigate the predicted resource starvation condition.Type: GrantFiled: March 31, 2021Date of Patent: April 23, 2024Assignee: McAfee LLCInventors: Raghavendra Satyanarayana Hebbalalu, Dattatraya Kulkarni, Srikanth Nalluri, Partha Sarathi Barik, Raja Sinha, Anjan Kumar Nayak
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Publication number: 20240114048Abstract: A computer-implemented method provides security services to an enterprise. The method computes, for a plurality of enterprise users, a plurality of user health scores based on respective protection statuses for a plurality of enterprise assets owned by respective users; computes, for the enterprise, an overall enterprise security status score based on the plurality of user health scores; graphically displays to an enterprise administrator the overall enterprise security status score; and presents to the enterprise administrator a plurality of action recommendations to improve the overall enterprise security status score.Type: ApplicationFiled: December 23, 2022Publication date: April 4, 2024Applicant: McAfee, LLCInventors: Dattatraya Kulkarni, Srikanth Nalluri, Himanshu Srivastava, Shashank Jain, Urmil Mahendra Parikh, Raghavendra Satyanarayana Hebbalalu, Piyush Pramod Joshi, Partha Sarathi Barik, Purushothaman Balamurugan, Saravana Kumar Ramalingam, Devanshi Saxena, Martin Pivetta, Sujay Subrahmanya, Shahmeet Singh, Ryan Burrows
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Patent number: 11934350Abstract: Disclosed examples include receiving an indication that a file is designated as a favorite file from a user device; retrieving the file from a remote location; storing the file as a first favorite file on a favorites storage device; re-retrieving the file from the remote location; and updating the first favorite file with the re-retrieved file.Type: GrantFiled: December 28, 2018Date of Patent: March 19, 2024Assignee: McAfee, LLCInventors: Kranthikumar Gadde, Mitesh Kumar, Kamlesh Halder, Raj Vardhan, Srikanth Nalluri, Dattatraya Kulkarni, Susmita Nayak, Krishnapur Venkatasubrahmanyam
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Patent number: 11921764Abstract: A device may receive, in near-real time, unstructured data associated with an application or a system, and may extract textual data from the unstructured data. The device may parse the textual data to generate parsed textual data, and may perform natural language processing on the parsed textual data to generate processed textual data. The device may process the processed textual data, with a clustering model, to identify topical data associated with the processed textual data, and may process the topical data, with a classification model, to group the topical data into categories. The device may generate a knowledge graph based on the categories, and may store the knowledge graph in a data structure. The knowledge graph may enable the device to provide answers to questions associated with the application or the system.Type: GrantFiled: March 12, 2020Date of Patent: March 5, 2024Assignee: Accenture Global Solutions LimitedInventors: Rajendra Prasad Tanniru, Aditi Kulkarni, Koushik M Vijayaraghavan, Srikanth Prasad, Jayashri Sridevi, Roopalaxmi Manjunath, Shankaranand Mallapur, Rajesh Nagarajan, Purnima Jagannathan, Abhijit Avinash Kulkarni, Joydeep Sarkar, Pareshkumar Ramchandbhai Gelot, Sudhir Hanumanthappa
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Patent number: 11924221Abstract: Mechanisms for authorizing requests to access a resource are provided, the methods comprising: receiving a request to access the resource at a hardware processor from an Internet Protocol (IP) address; determining whether a rule applies to the request to access the resource; in response to determining that a rule does not apply to the request to access the resource, sending a request for authorization; receiving a response to the request for authorization; and in response to the response to the request for authorization indicating that access is authorized, providing a connection to the resource.Type: GrantFiled: October 1, 2020Date of Patent: March 5, 2024Assignee: McAfee, LLCInventors: Harsha R. Joshi, Dattatraya Kulkarni, Srikanth Nalluri
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Publication number: 20240070314Abstract: A method includes receiving privacy information about an entity from a privacy resource; parsing the privacy information into a plurality of attributes of a user; calculating a privacy exposure index, at least in part based on each of the plurality of attributes; and transmitting the privacy exposure index.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: McAfee, LLCInventors: Ram Sharan Singh, Srikanth Nalluri, Dattatraya Kulkarni
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Publication number: 20240070313Abstract: A method includes receiving privacy information about an entity from a privacy resource; parsing the privacy information to identify a plurality of keywords; determining a plurality of attributes of a user requested by the entity, at least in part based on the plurality of keywords; and transmitting a result, at least in part based on the plurality of attributes.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: McAfee, LLCInventors: Ram Sharan Singh, Srikanth Nalluri, Dattatraya Kulkarni
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Patent number: 11822814Abstract: A storage device includes multiple memory dies and a controller configured to: (i) perform XOR parity computations for parity bins based, at least in part, on updated contents of a first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, (ii) storing the first parity data into a first parity memory cell associated with the first parity bin; (iii) identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin; (iv) copy the second parity memory cell to a third memory cell of the plurality of memory cells; and (v) associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.Type: GrantFiled: February 28, 2022Date of Patent: November 21, 2023Assignee: Western Digital Technologies, Inc.Inventors: Shrinidhi Srikanth Kulkarni, Vinayak Bhat
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Publication number: 20230369234Abstract: A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Yangyang SUN, Srikanth KULKARNI, Lily ZHAO, Milind SHAH
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Publication number: 20230273745Abstract: A storage device includes multiple memory dies and a controller configured to: (i) perform XOR parity computations for parity bins based, at least in part, on updated contents of a first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, (ii) storing the first parity data into a first parity memory cell associated with the first parity bin; (iii) identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin; (iv) copy the second parity memory cell to a third memory cell of the plurality of memory cells; and (v) associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Shrinidhi Srikanth Kulkarni, Vinayak Bhat
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Patent number: 11742253Abstract: An integrated circuit (IC) package that is to be incorporated into a computing device may include a metallization structure with circuits and/or other elements such as capacitors or inductors thereon. Pads for input/output (I/O) (or other) purposes may also be present at different locations on the metallization structure. Exemplary aspects of the present disclosure allow mold material to be placed over the circuits and/or other elements in readily-customizable configurations so as to allow placement of the I/O pads in any desired location on the metallization structure. Specifically, before the mold material is applied to the metallization structure, a mask material such as tape may be applied to portions of the metallization structure that contain I/O pads or otherwise have reasons to not have mold material thereon. The mold material is applied, and the mask material is removed, taking unwanted mold material with the mask material.Type: GrantFiled: December 3, 2020Date of Patent: August 29, 2023Assignee: QUALCOMM INCORPORATEDInventors: Sayok Chattopadhyay, Rajneesh Kumar, Srikanth Kulkarni
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Patent number: 11211263Abstract: Certain aspects of the present disclosure provide apparatus and techniques for partially molding packages for integrated circuits. A packaged assembly for integrated circuits includes: a substrate having at least one mold barrier between a first region on a first surface of the substrate and a second region on the first surface; a die attached to the substrate; one or more components attached to the substrate in the first region; and a first encapsulant over the one or more components in the first region, wherein the at least one mold barrier is configured to block a portion of the first encapsulant from moving from the first region of the substrate to the second region of the substrate during an application of the first encapsulant.Type: GrantFiled: November 19, 2019Date of Patent: December 28, 2021Assignee: QUALCOMM IncorporatedInventors: Srikanth Kulkarni, Rajneesh Kumar, Sayok Chattopadhyay
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Publication number: 20210351096Abstract: An integrated circuit (IC) package that is to be incorporated into a computing device may include a metallization structure with circuits and/or other elements such as capacitors or inductors thereon. Pads for input/output (I/O) (or other) purposes may also be present at different locations on the metallization structure. Exemplary aspects of the present disclosure allow mold material to be placed over the circuits and/or other elements in readily-customizable configurations so as to allow placement of the I/O pads in any desired location on the metallization structure. Specifically, before the mold material is applied to the metallization structure, a mask material such as tape may be applied to portions of the metallization structure that contain I/O pads or otherwise have reasons to not have mold material thereon. The mold material is applied, and the mask material is removed, taking unwanted mold material with the mask material.Type: ApplicationFiled: December 3, 2020Publication date: November 11, 2021Inventors: Sayok Chattopadhyay, Rajneesh Kumar, Srikanth Kulkarni
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Publication number: 20210280507Abstract: A package comprising a substrate comprising a first surface and a second surface, a passive device coupled to the first surface of the substrate, a first encapsulation layer located over the first surface of the substrate, wherein the first encapsulation layer encapsulates the passive device, an integrated device coupled to the second surface of the substrate, a second encapsulation layer located over the second surface of the substrate, wherein the second encapsulation layer encapsulates the integrated device, a plurality of through encapsulation layer interconnects coupled to the substrate, a plurality of encapsulation layer interconnects coupled to the plurality of through encapsulation layer interconnects, and at least one dummy interconnect located in the second encapsulation layer, wherein the at least one dummy interconnect is located vertically over a back side of the integrated device.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Manuel ALDRETE, Milind SHAH, Srikanth KULKARNI
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Publication number: 20210151330Abstract: Certain aspects of the present disclosure provide apparatus and techniques for partially molding packages for integrated circuits. A packaged assembly for integrated circuits includes: a substrate having at least one mold barrier between a first region on a first surface of the substrate and a second region on the first surface; a die attached to the substrate; one or more components attached to the substrate in the first region; and a first encapsulant over the one or more components in the first region, wherein the at least one mold barrier is configured to block a portion of the first encapsulant from moving from the first region of the substrate to the second region of the substrate during an application of the first encapsulant.Type: ApplicationFiled: November 19, 2019Publication date: May 20, 2021Inventors: Srikanth KULKARNI, Rajneesh KUMAR, Sayok CHATTOPADHYAY
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Patent number: 10056294Abstract: Semiconductor devices are described that employ techniques configured to control adhesive application between a substrate and a die. In an implementation, a sacrificial layer is provided on a top surface of the die to protect the surface, and bonds pads thereon, from spill-over of the adhesive. The sacrificial layer and spill-over adhesive are subsequently removed from the die and/or chip carrier. In an implementation, the die includes a die attach film (DAF) on a bottom surface of the die for adhering the die to the cavity of the substrate. The die is applied to the cavity with heat and pressure to cause a portion of the die attach film (DAF) to flow from the bottom surface of the die to a sloped surface of the substrate cavity.Type: GrantFiled: July 8, 2014Date of Patent: August 21, 2018Assignee: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Vivek S. Sridharan, Srikanth Kulkarni, Khanh Tran
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Publication number: 20180196022Abstract: In accordance with some embodiments of the present invention, a gas sensor system is disclosed. In accordance with some embodiments, a system includes a glass substrate; a heater formed on the glass substrate; and a sensor formed adjacent the heater formed on the glass substrate. A method of forming a gas sensor system according to some embodiments includes providing a glass substrate; forming a heater on the glass substrate; and forming a sensor adjacent the heater on the glass substrate.Type: ApplicationFiled: January 12, 2017Publication date: July 12, 2018Inventors: Srikanth KULKARNI, Viresh PATEL, Jitesh SHAH, George DELTORO
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Publication number: 20170166442Abstract: A method of forming a plurality of sealed packages comprises providing a base including a base surface; providing a lid including a lid surface; positioning a plurality of spaced apart seal members along the base surface, the seal members being formed from a seal material including a fusible metal alloy; positioning the lid on the base with a plurality of spaced apart spacers positioned and extending between the base surface and the lid surface, the spacers maintaining the lid surface spaced apart from the seal members by a fluid gap, the spacers being made from a spacer material including a fusible metal alloy; creating a controlled environment around the base and the lid; and heating to melt the spacers and the seal material so that the seal members form a plurality of seal rings between the base surface and the lid surface.Type: ApplicationFiled: December 11, 2015Publication date: June 15, 2017Inventors: Srikanth Kulkarni, Viresh P. Patel