Patents by Inventor Srikanth Nittala
Srikanth Nittala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11683018Abstract: An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.Type: GrantFiled: September 17, 2021Date of Patent: June 20, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Mayank Devam, Venkata Aruna Srikanth Nittala, Abhishek Bandyopadhyay
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Publication number: 20230091543Abstract: An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Inventors: Mayank Devam, Venkata Aruna Srikanth Nittala, Abhishek Bandyopadhyay
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Patent number: 11545996Abstract: Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.Type: GrantFiled: August 24, 2021Date of Patent: January 3, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Roberto Sergio Matteo Maurino, Venkata Aruna Srikanth Nittala, Bhargav R. Vyas, Christopher Peter Hurrell, Andrew J. Thomas
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Patent number: 11394394Abstract: A gain stage, such as an amplifier, e.g., an instrumentation amplifier, can receive an input signal and adjust the level of the input signal, e.g., amplify or attenuate. An output voltage of the gain stage can be applied to a subsequent circuit. Using various techniques, a second stage of an instrumentation amplifier, which can include a transconductance stage that converts a current to a voltage that can be applied to an output node of the instrumentation amplifier, can be removed. Removal of such a second stage can allow an output current from the gain stage to be applied directly from a current output node to an input node of a subsequent circuit.Type: GrantFiled: March 17, 2021Date of Patent: July 19, 2022Assignee: Analog Devices International Unlimited CompanyInventor: Venkata Aruna Srikanth Nittala
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Patent number: 10840865Abstract: A reference buffer circuit comprises a dual-difference amplifier circuit including a first differential input, a second differential input, and a differential output that provides a differential reference signal; a first reference voltage coupled to a first input of the first differential input and a second reference voltage coupled to a first input of the second differential input; and wherein outputs of the differential output are connected by a feedback circuit path to second inputs of the first and second differential inputs.Type: GrantFiled: July 16, 2019Date of Patent: November 17, 2020Assignee: Analog Devices International Unlimited CompanyInventors: Debopam Banerjee, Venkata Aruna Srikanth Nittala
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Patent number: 10763881Abstract: A voltage reference noise filter is provided that substantially eliminates noise with minimal external components for any circuit where the reference load current is a constant load and the circuit uses external components that have values that may vary with temperature, over time, and the like. The drift on an output of a voltage reference due to variation of resistor of the external filter is mitigated by moving the external resistor onto the chip containing the circuit. The voltage drop across the resistor is digitally compensated by a scaling factor determined during calibration. When more than one converter is provided on the chip, a further adjustment to the outputs of the converters is made based on the number of converters powered on or off. Also, error in output of converters due to mismatch among the converters is digitally compensated by a further scaling factor.Type: GrantFiled: August 27, 2019Date of Patent: September 1, 2020Assignee: Analog Devices International Unlimited CompanyInventors: Venkata Aruna Srikanth Nittala, Abhilasha Kawle, Rajasekar Rajendran
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Patent number: 10461770Abstract: Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.Type: GrantFiled: June 22, 2018Date of Patent: October 29, 2019Assignee: Analog Devices Global Unlimited CompanyInventors: Avinash Gutta, Venkata Aruna Srikanth Nittala
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Patent number: 10224951Abstract: A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.Type: GrantFiled: September 26, 2016Date of Patent: March 5, 2019Assignee: Analog Devices GlobalInventors: Venkata Aruna Srikanth Nittala, Avinash Gutta
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Publication number: 20190020352Abstract: Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.Type: ApplicationFiled: June 22, 2018Publication date: January 17, 2019Inventors: Avinash Gutta, Venkata Aruna Srikanth Nittala
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Publication number: 20180302101Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.Type: ApplicationFiled: April 12, 2017Publication date: October 18, 2018Inventors: Avinash Gutta, Venkata Aruna Srikanth Nittala, Abhilasha Kawle
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Patent number: 10103744Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.Type: GrantFiled: April 12, 2017Date of Patent: October 16, 2018Assignee: Analog Devices GlobalInventors: Avinash Gutta, Venkata Aruna Srikanth Nittala, Abhilasha Kawle
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Patent number: 9893877Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.Type: GrantFiled: October 27, 2016Date of Patent: February 13, 2018Assignee: Analog Devices GlobalInventors: Mayur Gurunath Anvekar, Venkata Aruna Srikanth Nittala, Roberto Sergio Matteo Maurino, Naiqian Ren
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Publication number: 20170207907Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.Type: ApplicationFiled: October 27, 2016Publication date: July 20, 2017Inventors: Mayur Gurunath Anvekar, Venkata Aruna Srikanth Nittala, Roberto Sergio Matteo Maurino, Naiqian Ren
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Publication number: 20170201270Abstract: A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.Type: ApplicationFiled: September 26, 2016Publication date: July 13, 2017Inventors: Venkata Aruna Srikanth Nittala, Avinash Gutta
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Patent number: 9294037Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.Type: GrantFiled: March 24, 2014Date of Patent: March 22, 2016Assignee: Analog Devices GlobalInventors: Roberto S. Maurino, Venkata Aruna Srikanth Nittala, Abhilasha Kawle, Sanjay Rajasekhar
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Publication number: 20150270805Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.Type: ApplicationFiled: March 24, 2014Publication date: September 24, 2015Applicant: Analog Devices TechnologyInventors: Roberto S. Maurino, Venkata Aruna Srikanth Nittala, Abhilasha Kawle, Sanjay Rajasekhar
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Patent number: 9065477Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.Type: GrantFiled: February 12, 2014Date of Patent: June 23, 2015Assignee: ANALOG DEVICES GLOBALInventors: Sanjay Rajasekhar, Abhilasha Kawle, Roberto S Maurino, Srikanth Nittala
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Publication number: 20150061908Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.Type: ApplicationFiled: February 12, 2014Publication date: March 5, 2015Applicant: ANALOG DEVICES TECHNOLOGYInventors: Sanjay RAJASEKHAR, Abhilasha KAWLE, Roberto S. MAURINO, Srikanth NITTALA
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Patent number: 8769364Abstract: A method for correcting digital gain error for a digital code includes receiving the digital code, generating a random number, adding a first dither to the digital code, in which a magnitude of the first dither is determined based on the random number, performing an operation on the digital code including the added dither with a factor to generate a scaled digital code, and subtracting a second dither corresponding to the first dither from the scaled digital code.Type: GrantFiled: October 20, 2011Date of Patent: July 1, 2014Assignee: Analog Devices, Inc.Inventor: Srikanth Nittala
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Publication number: 20130103998Abstract: A method for correcting digital gain error for a digital code includes receiving the digital code, generating a random number, adding a first dither to the digital code, in which a magnitude of the first dither is determined based on the random number, performing an operation on the digital code including the added dither with a factor to generate a scaled digital code, and subtracting a second dither corresponding to the first dither from the scaled digital code.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Applicant: ANALOG DEVICES, INC.Inventor: Srikanth NITTALA