Abstract: A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to the shared bus. The bus arbitrator comprises: 1) an input interface for receiving a first bus access request signal from a first bus device; 2) a delay circuit that receives the first bus access request signal from the input interface and generates a time-delayed first bus access request signal; and 3) a comparator circuit that receives the first bus access request signal from the input interface and the time-delayed first bus access request signal from the delay circuit and generates a line driver enable signal only if both of the first bus access request signal and the time-delayed first bus access request signal are enabled. The comparator circuit disables the line driver enable signal if either of the first bus access request signal or the time-delayed first bus access request signal is disabled.

Abstract: A clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK1 and CLK2, where no assumptions are made regarding frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START1 and START2 (both active high), are used to start and stop the clocks. As long as one clock is active, the START signal of the other clock will not have any effect. The invention includes interlock circuitry that ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signal.

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and ?V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and ?V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (?V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage.

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and −V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and −V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (−V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage.

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and −V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and −V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (−V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage.

Abstract: A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to the shared bus. The bus arbitrator comprises: 1) an input interface for receiving a first bus access request signal from a first bus device; 2) a delay circuit that receives the first bus access request signal from the input interface and generates a time-delayed first bus access request signal; and 3) a comparator circuit that receives the first bus access request signal from the input interface and the time-delayed first bus access request signal from the delay circuit and generates a line driver enable signal only if both of the first bus access request signal and the time-delayed first bus access request signal are enabled. The comparator circuit disables the line driver enable signal if either of the first bus access request signal or the time-delayed first bus access request signal is disabled.

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and −V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and −V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and too discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (−V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage.

Abstract: A clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK1 and CLK2, where no assumptions are made regarding frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START1 and START2 (both active high), are used to start and stop the clocks. As long as one clock is active, the START signal of the other clock will not have any effect. The invention includes interlock circuitry that ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signal.