Abstract: This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector. The computing system can inject a fault at a first node of the simulated integrated circuit design, which prompts alarm logic to trigger indicating a detection of the injected fault. The computing system, in response to the triggering of the alarm logic, can initiate back-propagation to identify which intermediate nodes of the simulated integrated circuit design, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger. The computing system can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.

Abstract: This application discloses a computing system implementing a functional safety validation tool to locate a vulnerable section of an electronic system described in a circuit design, select safety circuitry configured to monitor the vulnerable section of the electronic system, and modify the circuit design by inserting the safety circuitry and control circuitry into the circuit design. The control circuitry and the safety circuitry can detect faults in the vulnerable section of the electronic system. The functional safety validation tool can generate a logical equivalency check script for the modified circuit design, wherein a logical equivalency checking tool can be utilized to determine whether the modified circuit design is logically equivalent to the circuit design. The functional safety validation tool can generate a test bench for the modified circuit design, wherein at least one verification tool can be utilized in a verification environment to simulate the modified circuit design.

Abstract: A computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

Abstract: This application discloses a computing system implementing a functional safety validation tool to locate a vulnerable section of an electronic system described in a circuit design, select safety circuitry configured to monitor the vulnerable section of the electronic system, and modify the circuit design by inserting the safety circuitry and control circuitry into the circuit design. The control circuitry and the security circuitry can detect faults in the vulnerable section of the electronic system. The functional safety validation tool can generate a logical equivalency check script for the modified circuit design, which a logical equivalency checking tool can utilize to determine whether the modified circuit design is logically equivalent to the circuit design. The functional safety validation tool can generate a test bench for the modified circuit design, which at least one verification tool can utilize in a verification environment to simulate the modified circuit design.

Abstract: This application discloses a computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

Abstract: This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector. The computing system can inject a fault at a first node of the simulated integrated circuit design, which prompts alarm logic to trigger indicating a detection of the injected fault. The computing system, in response to the triggering of the alarm logic, can initiate back-propagation to identify which intermediate nodes of the simulated integrated circuit design, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger. The computing system can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.

Abstract: An apparatus includes an input module and a color synthesis module. The input module is configured to receive mosaic image data representing an image. The mosaic image data includes radial distortion. The color synthesis module, implemented in digital electronic circuitry, includes a radial distortion correction module and a synthesis module. The radial distortion correction module is configured to receive the mosaic image data and generate correction data to correct the radial distortion in the mosaic image data. The synthesis module is configured to receive the mosaic image data and the correction data, wherein the mosaic image data includes a plurality of input pixel values and respective input pixel locations prior to being corrected, and generate demosaiced image data using the mosaic image data and the correction data.

Abstract: Apparatus having corresponding methods and computer programs comprise an input module to receive image data representing an image, wherein the image data includes radial distortion; and a zoom module to scale the image based on the image data and a scaling factor, wherein the zoom module comprises a radial distortion correction module to correct the radial distortion in the image data while the zoom module scales the image.

Abstract: A method and system for rendering a frame to be displayed on a screen includes a memory-sink mechanism configured to store a copy of a screen image in memory, a snoop mechanism configured to monitor a system parameter, a controller configured to switch between first and second operation modes in response to the snoop mechanism detecting a change to the system parameter, and a rendering mechanism to retrieve the copy of the screen image when the system operates in the second mode of operation.

Abstract: A system, apparatus, method, and article to reduce display bandwidth are described. The apparatus may include a display controller to identify an opaque region in windows defining an output image. The display controller determines an overlay order for any overlapping portions of the windows. A higher order window overlays a lower order window. The display controller fetches data defining the opaque region only from an uppermost overlay window prior to displaying the output image.

Abstract: A system and method predict when to generate a bus request ahead-of-time based on bus-activity, bus-usage efficiency and bus-bandwidth usage. A bus-usage efficiency indicator may be generated by a requester, such as a memory controller, based on a number of unused bus cycles that were granted to the requestor during a prior observation window. The bus-bandwidth usage indicator may be generated by the requestor based on a number of bus transactions effectively utilized by the requester during the prior observation window. The bus-activity indicator may be received from a bus arbiter to indicate system bus activity during a prior system-bus observation window. When the bus-activity indicator indicates that the system bus is busy, a requester may transition between a full-speculation state, a delayed speculation state and a no-speculation state based on bus-usage efficiency and bandwidth usage. When the system bus is idle, a requestor may remain in the full-speculation state.

Abstract: A system and method predict when to generate a bus request ahead-of-time based on bus-activity, bus-usage efficiency and bus-bandwidth usage. A bus-usage efficiency indicator may be generated by a requester, such as a memory controller, based on a number of unused bus cycles that were granted to the requester during a prior observation window. The bus-bandwidth usage indicator may be generated by the requester based on a number of bus transactions effectively utilized by the requester during the prior observation window. The bus-activity indicator may be received from a bus arbiter to indicate system bus activity during a prior system-bus observation window. When the bus-activity indicator indicates that the system bus is busy, a requestor may transition between a full-speculation state, a delayed speculation state and a no-speculation state based on bus-usage efficiency and bandwidth usage. When the system bus is idle, a requester may remain in the full-speculation state.

Abstract: A system and method predict when to generate a bus request ahead-of-time based on bus-activity, bus-usage efficiency and bus-bandwidth usage. A bus-usage efficiency indicator may be generated by a requester, such as a memory controller, based on a number of unused bus cycles that were granted to the requester during a prior observation window. The bus-bandwidth usage indicator may be generated by the requester based on a number of bus transactions effectively utilized by the requester during the prior observation window. The bus-activity indicator may be received from a bus arbiter to indicate system bus activity during a prior system-bus observation window. When the bus-activity indicator indicates that the system bus is busy, a requestor may transition between a full-speculation state, a delayed speculation state and a no-speculation state based on bus-usage efficiency and bandwidth usage. When the system bus is idle, a requester may remain in the full-speculation state.

Abstract: A bus arbitration scheme may include a bus arbiter that grants bus requests based on a combination of both hierarchical ranking and age, where age is an indication of a time interval since a bus request was made but not granted. The hierarchical rankings and the manner in which rankings and age are combined may be programmable. These techniques may also be combined with other arbitration techniques.