Patents by Inventor Srikanth Srihari

Srikanth Srihari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11605710
    Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: March 14, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Uzma B. Rana, Anthony K. Stamper, Steven M. Shank, Srikanth Srihari
  • Publication number: 20220190108
    Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.
    Type: Application
    Filed: January 22, 2021
    Publication date: June 16, 2022
    Inventors: Uzma B. Rana, Anthony K. Stamper, Steven M. Shank, Srikanth Srihari
  • Patent number: 9479160
    Abstract: An SPDT switch in a RF communication transceiver provides for choosing the transmit/receive path for the RF signal. It consists of the series and shunt branches each consisting of stack of FETs. Performance metrics of the RF switch are insertion loss and isolation. At high frequency, the device/FET capacitance and the parasitic capacitances provide a leakage path for the signal, resulting in higher insertion loss and lower isolation. A parallel resonant LC network across each of the series and/or shunt branch FETs in a SPDT switch provides lower insertion loss, higher switch isolation, and lower out of band harmonics when compared to that of the state of the art SPDT switch. A method to reduce the form factor of such switch configuration is disclosed which is useful in wireless front end modules.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 25, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Srikanth Srihari, Venkata N. R. Vanukuru
  • Publication number: 20160182037
    Abstract: An SPDT switch in a RF communication transceiver provides for choosing the transmit/receive path for the RF signal. It consists of the series and shunt branches each consisting of stack of FETs. Performance metrics of the RF switch are insertion loss and isolation. At high frequency, the device/FET capacitance and the parasitic capacitances provide a leakage path for the signal, resulting in higher insertion loss and lower isolation. A parallel resonant LC network across each of the series and/or shunt branch FETs in a SPDT switch provides lower insertion loss, higher switch isolation, and lower out of band harmonics when compared to that of the state of the art SPDT switch. A method to reduce the form factor of such switch configuration is disclosed which is useful in wireless front end modules.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Srikanth Srihari, Venkata N. R. Vanukuru