Abstract: A system or method for offloading data operations to a field programmable gate array (FPGA), that includes loading, by the FPGA, a descriptor ring, performing a first lookup, in the descriptor ring, to identify a first descriptor entry, identifying, in the first descriptor entry, a first data operation, making a first determination that the first data operation is unavailable in any of a plurality of module slots of the FPGA, and based on the first determination, loading a first operation module, matching the first data operation, into a first swappable module slot of the plurality of module slots.

Abstract: A Logically Composed System (LCS) resource device presentation system include an orchestrator device coupled to a host processing system and a first resource device. The orchestrator device programs the orchestrator device with first configuration information that provides a first emulated resource device for the first resource device, and programs a memory system in the orchestrator device to provide a first emulated device controller for the first emulated resource device. The orchestrator device then presents the first emulated resource device to the host processing system. The orchestrator device may then use the first emulated device controller and the first configuration information to cause the first resource device to perform at least one first operation for the processing system.

Abstract: An LCS resource device utilization system includes an orchestrator device coupled to a processing system, a memory system, and resource device. The orchestrator device receives an LCS provisioning instruction to provide an LCS using the resource devices and, in response, emulates respective hot plug events for an operating system provided for the LCS using the processing system and between emulated resource devices for the resource devices that are provided via the orchestrator device and respective emulated ports on emulated switch device(s) that are presented to the operating system. The orchestrator device then receives an LCS stop provisioning instruction to stop providing the LCS and, in response, emulates respective hot removal events for the operating system and between the emulated resource devices and the respective emulated ports on the emulated switch device(s) that are presented to the operating system.

Abstract: An information handling system includes a publisher device and an offload device. Multiple subscriber devices are associated with the publisher device. The offload device communicates with the publisher device. The offload device receives a packet transmission from the publisher device, and translates a topic address of the packet transmission to multiple destination addresses. The offload device sends the packet transmission to each of the subscriber devices. Each of the subscriber devices is associated with a corresponding destination address of the multiple destination address. The offload device receives one or more acknowledgements from the subscriber devices, and combines the one or more acknowledgements into a composite completion message. The offload device sends the composite completion message to the publisher device.

Abstract: An information handling system includes a publisher device and an offload device. Multiple subscriber devices are associated with the publisher device. The offload device communicates with the publisher device. The offload device receives a packet transmission from the publisher device, and translates a topic address of the packet transmission to multiple destination addresses. The offload device sends the packet transmission to each of the subscriber devices. Each of the subscriber devices is associated with a corresponding destination address of the multiple destination address. The offload device receives one or more acknowledgements from the subscriber devices, and combines the one or more acknowledgements into a composite completion message. The offload device sends the composite completion message to the publisher device.

Abstract: Systems and methods for I/O acceleration in a virtualized system include receiving, at a hypervisor from an application executing under a guest OS, a request to write new data to a RAID system, redirecting the request to the VSA owning the RAID drives, moving the new data from guest OS physical address space to VSA physical address space, preparing, by a RAID driver in the VSA, the new data for writing according to a RAID redundancy policy, reading, by the RAID driver into a first buffer, old data and old parity information, performing, by an architectural data mover, inline XOR copy operations to compute a difference between the old and new data, compute new parity information, and write the difference and new parity information into the second buffer, and writing, by the RAID driver, the difference and new parity information to the RAID system using the redundancy policy.

Abstract: Systems and methods for I/O acceleration in a virtualized system include receiving, at a hypervisor from an application executing under a guest OS, a request to write new data to a RAID system, redirecting the request to the VSA owning the RAID drives, moving the new data from guest OS physical address space to VSA physical address space, preparing, by a RAID driver in the VSA, the new data for writing according to a RAID redundancy policy, reading, by the RAID driver into a first buffer, old data and old parity information, performing, by an architectural data mover, inline XOR copy operations to compute a difference between the old and new data, compute new parity information, and write the difference and new parity information into the second buffer, and writing, by the RAID driver, the difference and new parity information to the RAID system using the redundancy policy.

Abstract: An information handling system reduces latency of input/output transactions. The information handling system includes a system memory and an accelerator. The accelerator intercepts a command response that is issued by the system memory, determines a correct drive from an incorrect drive based on an attribute of the command response, and maps an address of the command response and sends the command response to the correct drive. The no-response command is sent to the incorrect drive. The correct drive completes the command response, and the incorrect drive issues a response that is disregarded by the accelerator.

Abstract: A queue-based non-volatile memory (NVM) hardware assist card, information handling system, and method are disclosed herein.

Abstract: An information handling system reduces latency of input/output transactions. The information handling system includes a system memory and an accelerator. The accelerator intercepts a command response that is issued by the system memory, determines a correct drive from an incorrect drive based on an attribute of the command response, and maps an address of the command response and sends the command response to the correct drive. The no-response command is sent to the incorrect drive. The correct drive completes the command response, and the incorrect drive issues a response that is disregarded by the accelerator.

Abstract: An information handling system includes an accelerator that advertises, via a single peripheral component interconnect express endpoint, to a processor a plurality of queues from different drives. The processor writes commands and maps each command to target a particular one of the queues. The accelerator performs a queue level logical separation for the mapped command to be processed by the target queue.

Abstract: A queue-based non-volatile memory (NVM) hardware assist card, information handling system, and method are disclosed herein.

Abstract: An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.

Abstract: An information handling system includes a processor configured to write a first command stride and a second command stride. Each of the first command stride and the second command stride includes logical commands in a single queue, and each of the logical commands is mapped for processing by a peripheral component interconnect express (PCIe). An accelerator may perform a logical separation of the logical commands based on the mapping of each logical command, wherein the logical commands are processed in parallel by the PCIe drives.

Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a plurality of memory storage devices communicatively coupled to the hardware logic device, a plurality of command fetch requests; analyzing metadata associated with each of the plurality of command fetch requests in order to serialize the plurality of command fetch requests in a chronological order; and communicating the coalesced command fetch requests in the chronological order to a memory having stored thereon commands responsive to the coalesced command fetch requests.

Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor subsystem having access to a memory subsystem and a device communicatively coupled to the processor subsystem, the device having an endpoint assigned for access by an operating system executing on the processor subsystem such that the endpoint appears to the operating system as a logical hardware adapter, wherein the device is configured to discover a private device coupled to the device, enumerate the private device as a managed device of the device, and map a portion of a virtual address space of an operating system executing on the processor subsystem to the private device, such that the private device is abstracted to the operating system as a virtual memory address of the operating system.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor subsystem having access to a memory subsystem and a device communicatively coupled to the processor subsystem, the device having an endpoint assigned for access by an operating system executing on the processor subsystem such that the endpoint appears to the operating system as a logical hardware adapter, wherein the device is configured to discover a private device coupled to the device, enumerate the private device as a managed device of the device, and map a portion of a virtual address space of an operating system executing on the processor subsystem to the private device, such that the private device is abstracted to the operating system as a virtual memory address of the operating system.

Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a plurality of memory storage devices communicatively coupled to the hardware logic device, a plurality of command fetch requests; analyzing metadata associated with each of the plurality of command fetch requests in order to serialize the plurality of command fetch requests in a chronological order; and communicating the coalesced command fetch requests in the chronological order to a memory having stored thereon commands responsive to the coalesced command fetch requests.

Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.