Patents by Inventor Srilatha Manne
Srilatha Manne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359912Abstract: A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.Type: ApplicationFiled: July 13, 2023Publication date: November 9, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
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Patent number: 11755941Abstract: A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.Type: GrantFiled: August 8, 2022Date of Patent: September 12, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Poulami Das, Nicolas Guillaume Delfosse, Christopher Anand Pattison, Srilatha Manne, Douglas Carmean, Krysta Marie Svore, Helmut Gottfried Katzgraber
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Patent number: 11645209Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.Type: GrantFiled: August 3, 2021Date of Patent: May 9, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
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Publication number: 20220385306Abstract: A quantum computing device comprises a surface code lattice that includes/logical qubits, where/is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the/logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
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Patent number: 11410070Abstract: A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.Type: GrantFiled: November 18, 2019Date of Patent: August 9, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Poulami Das, Nicolas Guillaume Delfosse, Christopher Anand Pattison, Srilatha Manne, Douglas Carmean, Krysta Marie Svore, Helmut Gottfried Katzgraber
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Publication number: 20210365378Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
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Patent number: 11093405Abstract: A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.Type: GrantFiled: May 29, 2019Date of Patent: August 17, 2021Assignee: MARVELL ASIA PTE, LTD.Inventors: Shubhendu S. Mukherjee, David H. Asher, Richard E. Kessler, Srilatha Manne
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Patent number: 11080195Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.Type: GrantFiled: September 10, 2019Date of Patent: August 3, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
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Publication number: 20210081323Abstract: The hit rate of a L1 icache when operating with large programs is substantially improved by reserving a section of the L1 icache for regular instructions and a section for non-instruction information. Instructions are prefetched for storage in the instruction section of the L1 icache based on information in the non-instruction section of the L1 icache.Type: ApplicationFiled: September 12, 2019Publication date: March 18, 2021Inventors: Edward MCLELLAN, Alexander RUCKER, Shay GAL-ON, Srilatha MANNE
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Publication number: 20210073132Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.Type: ApplicationFiled: September 10, 2019Publication date: March 11, 2021Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
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Publication number: 20210042652Abstract: A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.Type: ApplicationFiled: November 18, 2019Publication date: February 11, 2021Applicant: Microsoft Technology Licensing, LLCInventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
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Publication number: 20210042651Abstract: A quantum computing device comprises at least one quantum register including l logical qubits, where l is a positive integer. The quantum computing device further includes a set of d decoder blocks coupled to the at least one quantum register, where d<2*l. In this way, the decoder blocks may share decoding requests generated by the logical qubits.Type: ApplicationFiled: November 18, 2019Publication date: February 11, 2021Applicant: Microsoft Technology Licensing, LLCInventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
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Publication number: 20210042650Abstract: A quantum computing device comprises at least one quantum register including a plurality of qubits, and a hardware decoder. The hardware decoder is configured to: receive syndrome data from one or more of the plurality of qubits; and decode the received syndrome data by implementing a Union-Find decoding algorithm via a hardware microarchitecture including two or more pipeline stages.Type: ApplicationFiled: November 15, 2019Publication date: February 11, 2021Applicant: Microsoft Technology Licensing, LLCInventors: Poulami DAS, Nicolas Guillaume DELFOSSE, Christopher Anand PATTISON, Srilatha MANNE, Douglas CARMEAN, Krysta Marie SVORE, Helmut Gottfried KATZGRABER
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Patent number: 10558577Abstract: Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.Type: GrantFiled: June 18, 2018Date of Patent: February 11, 2020Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Srilatha Manne
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Patent number: 10281964Abstract: A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. Some embodiments of the controller can control a performance state of the processing system based on the peak temperature and the thermal time constant for heating of the processing system.Type: GrantFiled: January 29, 2016Date of Patent: May 7, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Can Hankendi, Manish Arora, Indrain Paul, Wei Huang, Srilatha Manne
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Patent number: 10133678Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.Type: GrantFiled: August 28, 2013Date of Patent: November 20, 2018Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Yasuko Eckert, Syed Ali Jafri, Srilatha Manne, Gabriel Loh
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Publication number: 20180300247Abstract: Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.Type: ApplicationFiled: June 18, 2018Publication date: October 18, 2018Inventors: Shubhendu Sekhar MUKHERJEE, David Albert CARLSON, Srilatha MANNE
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Patent number: 10025361Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.Type: GrantFiled: June 5, 2014Date of Patent: July 17, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Indrani Paul, Vignesh Trichy Ravi, Manish Arora, Srilatha Manne
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Patent number: 10013357Abstract: Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.Type: GrantFiled: September 19, 2016Date of Patent: July 3, 2018Assignee: Cavium, Inc.Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Srilatha Manne
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Patent number: 10007614Abstract: System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.Type: GrantFiled: February 2, 2016Date of Patent: June 26, 2018Assignee: Cavium, Inc.Inventors: Xiaodong Wang, Srilatha Manne, Bryan Wai Chin, Isam Akkawi, David Asher