Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set.

Abstract: Disclosed is an apparatus and method for testing an IC having a plurality of scan chains. A test input is transmitted over a tester channel to at least one scan chain during a time interval. Specifically, a memory element stores a first test input transmitted during a first time interval and a combinational circuit connected to the memory element and scan chain transmits to the scan chain one of a) the first test input and b) a second test input transmitted over the tester channel during a second time interval occurring after the first time interval.

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.

Abstract: A test output compaction architecture and method that takes advantage of a response shaper in order to minimize masking of faults during compaction. A response shaper is inserted between a plurality of scan chains and an output compactor. The response shaper receives output responses from scan chains and reshapes the output responses in a manner that minimizes masking of faults by the output compactor.

Abstract: Disclosed is a method and apparatus for improved delay fault testing by optimizing the order of scan cells in a scan chain. The order of the scan cells is determined by using a cost value for an order of scan cells, the cost value being computed from costs assigned to orderings of individual pairs of scan cells. These costs can be based on the number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain. The disclosed techniques allow for enhanced delay fault coverage by rearranging scan flip-flops without increasing routing overhead.

Abstract: Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

Abstract: A content-based information retrieval architecture is herein disclosed that can achieve correct and predictable high speed lookups while taking advantage of inexpensive conventional memory components. A content-based information retrieval architecture is herein disclosed that can achieve high speed lookups with a constant query time while taking advantage of inexpensive conventional memory components. In accordance with an embodiment of the invention, the architecture comprise a hashing module, a first table of encoded values, a second table of lookup values, and a third table of associated input values. The input value is hashed a number of times to generate a plurality of hashed values, the hashed values corresponding to locations of encoded values in the first table. The encoded values obtained from an input value encode an output value such that the output value cannot be recovered from any single encoded value.

Abstract: A method of creating models for power estimation of a circuit comprising generating an input space for the circuit. The input space is separated into multiple power modes corresponding to regions that display similar power behavior. Separate power models are generated for each of said multiple power modes. A power mode identification function is created that selects an appropriate power model from the separate power models based on the present and past values of the circuit inputs.

Abstract: Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

Abstract: A test system for a circuit board, wherein said circuit board has a plurality of cores such that at least one of said plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board.

Abstract: A method of generating a vector set, said vector set being used for testing sequential circuits. The method comprises selecting a plurality of fault models, identifying a fault list each for each of said plurality of fault models, identifying a vector set each for each of said fault lists, selecting a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit, compacting each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and creating a vector set by combining all vector sets compacted. A system and a computer program product for testing circuits with a compacted vector set where the compacted vector set is created by dropping faults based on a tolerance limit.

Abstract: A method of creating models for power estimation of a circuit comprising generating an input space for the circuit. The input space is separated into multiple power modes corresponding to regions that display similar power behavior. Separate power models are generated for each of said multiple power modes. A power mode identification function is created that selects an appropriate power model from the separate power models based on the present and past values of the circuit inputs.

Abstract: A method of solving a test generation problem for sequential circuits is disclosed. The method comprises recursively dividing an original test generation problem into smaller problems, wherein said sub-problems may be dependent while one or more of said dependent sub-problems may have solution-specific independence, finding solutions for said sub-problems, reusing solutions for dependent sub-problems, whenever the dependent sub-problems enjoy solution-specific independence; and identifying a minimal subset of conflicting objectives if a sub-problem that has to be solved to achieve multiple objectives has no solution. A test generation system comprising a computer, said computer having a cpu and memory, said memory comprising instructions capable of implementing components of said system.

Abstract: At-speed strategies for testing high speed designs on slower testers. At-speed testing schemes is provided that integrates the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. A slow tester that uses test vectors that are generated while taking into account the speed of the tester.

Abstract: A two phase vector restoration technique which extracts a minimal subsequence from a sequence that detects a chosen set of faults is provided. The disclosed vector restoration technique is useful in static compaction of test sequences and in fault diagnosis. An accelerated two phase vector restoration that provides further improvement is also provided. The present invention is a significant improvement over the state of the art in the following ways: (1) a sequence of length n can be restored with only O(n log2n) simulations while known approaches require simulation of O(n2) vectors, (2) a two-step restoration process is used that makes vector restoration practical for large designs, and (3) restoration process for several faults is overlapped to provide significant acceleration in vector restoration. The described vector restoration technique has been integrated into a static test sequence compaction system.

Abstract: A method to identify and test primitive faults in combinational circuits described as multi-level or two-level netlists. A primitive fault is a multiple path delay for which none of the single paths contained in the fault is robustly or non-robustly testable while the presence of the fault will degrade the circuit performance. Identification and testing of primitive faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The single-path delay faults contained in a primitive fault have to merge at some gate(s). The methodology for identifying primitive faults can quickly (1) rule out a large number of gates as possible merging points for primitive faults, and (2) reduce or prune the combination of paths that can never belong to any primitive fault.

Abstract: A technique for static compaction of test sequences is described. The method for static compaction according to the present invention includes two key features: (1) two-phase vector restoration, and (2) identification, pruning, and re-ordering of segments. Segments partition the compaction problem into sub-problems. Segments are identified, dynamically pruned and re-ordered to achieve further compaction and speed up.

Abstract: A synchronous test model (STM) and corresponding method capture the essential behavior of an asynchronous circuit under test. During operation of the method, (1) An STM for the asynchronous circuit is constructed assuming either a user-specified cycle length or an estimated cycle length; (2) a target fault list is created containing only faults in the asynchronous circuit, (3) test patterns are generated from the STM using a synchronous test generator; (4) the test patterns are translated into test sequences for the asynchronous circuit; and (5) the translated patterns are validated by fault simulation on the asynchronous circuit.

Abstract: A method to significantly accelerate sequential test generation algorithms by accurately computing signal constraints for large sequential circuits and using these constraints effectively during deterministic sequential test generation. The signal constraint computation technique is based on three key ideas: (1) unlike prior techniques (which compute line probabilities assuming only a 0 or 1 value for any signal), line probabilities are computed by allowing signals to assume values other than 0 or 1, (2) line justification techniques are employed to update line probabilities, and (3) symbolic simulation is iteratively used in conjunction with line probability computation and line justification to refine the set of values that a signal can assume. The method results in a significant reduction (more than 50%) in test generation time which is achieved without comprising the fault coverage than can be obtained.

Abstract: A method of circuit synthesis which considers all circuit configurations that can be designed utilizing a retiming with logic duplication (RLD) methodology. These circuit configurations (RLD configurations) each have significantly different area, performance and testability characteristics and are represented as a set of feasible solutions to an integer linear program (ILP). The ILP permits the evaluation of different design and testability metrics for each of the configurations. An approach to solve several useful special cases of the ILP in polynomial time and an application of RLD transformation to partial scan is shown. Using this method, a desired RLD configuration is produced having a minimal number of duplicated logic nodes.