Patents by Inventor Srinand Venkatesan

Srinand Venkatesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Link level retry scheme
    Patent number: 7991875
    Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra K. Mannava, Rajee S. Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar
  • Link level retry scheme
    Publication number: 20070130353
    Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
    Type: Application
    Filed: January 6, 2006
    Publication date: June 7, 2007
    Inventors: Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra Mannava, Rajee Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar
  • Link level retry scheme
    Patent number: 7016304
    Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: March 21, 2006
    Assignee: Intel Corporation
    Inventors: Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra K. Mannava, Rajee S. Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar
  • Link level retry scheme
    Publication number: 20020172164
    Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
    Type: Application
    Filed: May 18, 2001
    Publication date: November 21, 2002
    Inventors: Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra K. Mannava, Rajee S. Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar
  • Dual mode bus bridge for computer system
    Patent number: 6134622
    Abstract: A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently and a combined mode in which the first and second external buses are combined to create a single bus. The bus expander bridge includes a first set of data queues for routing data between the first external bus and the third bus, and a second set of data queues for routing data between the second external bus and the third bus. The bus expander bridge also includes a controller coupled to the first and second sets of data queues and operating the first and second sets of data queues in parallel for the independent mode. The controller routes even addressed data through the first set of data queues and routes odd addressed data through the second set of data queues for the combined mode.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: October 17, 2000
    Assignee: Intel Corporation
    Inventors: Suvansh Kapur, Kevin Koschoreck, Srinand Venkatesan, D. Michael Bell