Patents by Inventor Srinath Alturi

Srinath Alturi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Barrel compactor system, method and device
    Patent number: 9954551
    Abstract: A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 24, 2018
    Assignee: Cavium, Inc.
    Inventors: Premshanth Theivendran, Weihuang Wang, Sowmya Hotha, Srinath Alturi
  • Barrel compactor system, method and device having cell combination logic
    Patent number: 9584635
    Abstract: A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: February 28, 2017
    Assignee: Cavium, Inc.
    Inventors: Premshanth Theivendran, Weihuang Wang, Sowmya Hotha, Srinath Alturi
  • BARREL COMPACTOR SYSTEM, METHOD AND DEVICE
    Publication number: 20160294408
    Abstract: A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Premshanth Theivendran, Weihuang Wang, Sowmya Hotha, Srinath Alturi
  • BARREL COMPACTOR SYSTEM, METHOD AND DEVICE HAVING CELL COMBINATION LOGIC
    Publication number: 20160294988
    Abstract: A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Premshanth Theivendran, Weihuang Wang, Sowmya Hotha, Srinath Alturi
  • Hierarchical statistically multiplexed counters and a method thereof
    Patent number: 9413357
    Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: August 9, 2016
    Assignee: Cavium, Inc.
    Inventors: Weihuang Wang, Gerald Schmidt, Srinath Alturi, Weinan Ma, Shrikant Sundaram Lnu
  • HIERARCHICAL STATISTICALLY MULTIPLEXED COUNTERS AND A METHOD THEROF
    Publication number: 20150365355
    Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
    Type: Application
    Filed: June 11, 2014
    Publication date: December 17, 2015
    Inventors: Weihuang Wang, Gerald Schmidt, Srinath Alturi, Weinan Ma, Shrikant Sundaram Lnu