Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: Sub-micron-dimensioned, asymmetrically-configured MOS and/or CMOS transistors are fabricated using removable sidewall spacers made of a material, such as UV-nitride, one of which is selectively treated subsequent to deposition, e.g., by ion implantation, to augment the etch rate thereof with a room temperature etchant, e.g., dilute aqueous HF. The treated spacer is removed with the dilute, aqueous HF prior to implantation of asymmetrically-configured, moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.