Patents by Inventor Srinath Ramaswamy

Srinath Ramaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8842046
    Abstract: A loop antenna is provided. The apparatus comprises a substrate, a first metallization layer, and a second metallization layer. The substrate has first and second feed terminals and a ground terminal. The first metallization layer is disposed over the substrate and includes a first window conductive region, a first conductive region, a second conductive region, and a third conductive region. The first conductive region is disposed over and is in electrical contact with the first feed terminal; it is also is substantially circular and located within the first window region. The second conductive region is disposed over and is in electrical contact with the second feed terminal; it is also substantially circular and is located within the first window region. The a third conductive region is disposed over and is in electrical contact with the ground terminal, and the third conductive region substantially surrounds the first window region.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: September 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Eunyoung Seok, Brian P. Ginsburg, Baher Haroun, Srinath Ramaswamy, Vijay B. Rentala
  • Patent number: 8842055
    Abstract: An apparatus for emitting radiation is provided. The apparatus comprises an antenna formed on a substrate, and a high impedance surface (HIS). The HIS has a plurality of cells formed on the substrate that are arranged to form an array that substantially surrounds at least a portion of the antenna. Each cell generally includes a ground plane, first plate, second plate, and an interconnect. The ground plane is formed on the substrate, while the first plate (which is substantially rectangular) is formed over and coupled to the ground plane. The first plate for each cell is also arranged so as to form a first checkered pattern for the array. The second plate (which is substantially rectangular) is formed over and is substantially parallel to the first plate. The first and second plates are also substantially aligned with a central axis that extends generally perpendicular to the first and second plates hand have a interconnect formed therebetween.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: September 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James N. Murdock, Eunyoung Seok, Brian P. Ginsburg, Vijay B. Rentala, Srinath Ramaswamy, Baher Haroun
  • Publication number: 20140241581
    Abstract: A periphery band is around an excluded region. For automatically counting physical objects within the periphery band and the excluded region, an imaging sensor captures: a first image of the periphery band and the excluded region; and a second image of the periphery band and the excluded region. In response to the first image, a first number is counted of physical objects within the periphery band and the excluded region. Relevant motion is automatically detected within the periphery band, while ignoring motion within the excluded region. In response to the second image, a second number is counted of physical objects within the periphery band and the excluded region. In response to determining that a discrepancy exists between the detected relevant motion and the second number, the discrepancy is handled.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 28, 2014
    Inventors: Sriram Narayanan, Russell Rosenquist, Srinath Ramaswamy
  • Publication number: 20140111394
    Abstract: An apparatus is provided. In the apparatus, there is an antenna package and an integrated circuit (IC). A circuit trace assembly is secured to the IC. A coupler (with an antenna assembly and a high impedance surface (HIS)) is secured to the circuit trace assembly. An antenna assembly has a window region, a conductive region that substantially surrounds the window region, a circular patch antenna that is in communication with the IC, and an elliptical patch antenna that is located within the window region, that is extends over at least a portion of the circular patch antenna, and that is in communication with the circular patch antenna. The HIS substantially surrounds the antenna assembly.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Eunyoung Seok, Srinath Ramaswamy, Brian B. Ginsburg, Vijay B. Rentala, Baher Haroun
  • Publication number: 20130059551
    Abstract: An apparatus is provided. A plurality of transceiver antennas are arranged to form a phased array, where each antenna include a differential transmit antenna and a differential receive antenna arranged in a first pattern. A plurality of transceivers are arranged in a second pattern that is substantially symmetrical, and each transceiver is associated with at least one of the transceiver antennas and includes a feed network. Each feed network has a power amplifier (PA), a first matching network that is coupled between the PA and its associated transmit antenna so as to translate the phase of each differential transmit signal, a low noise amplifier (LNA), and a second matching network that is coupled between the LNA and its associated receive antenna so as to translate the phase of each differential receive signal.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Brian P. Ginsburg, Eunyoung Seok, Vijay B. Rentala, Srinath Ramaswamy, Baher Haroun
  • Publication number: 20130026586
    Abstract: An antenna is provided. This antenna is contained within a package that is secured to an IC (which allows radiation to propagated away for a printed circuit board so as to reduce interference), and this antenna includes two loop antennas that are shorted to ground and that “overlap” and includes a “via wall.” With this configuration, circular polarization can be achieved by varying the relative phases of the input signals, and the “via wall” improves efficiency by reducing surface waves.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Eunyoung Seok, Srinath Ramaswamy, Brian P. Ginsburg, Vijay B. Rentala, Baher Haroun
  • Publication number: 20130021208
    Abstract: A loop antenna is provided. The apparatus comprises a substrate, a first metallization layer, and a second metallization layer. The substrate has first and second feed terminals and a ground terminal. The first metallization layer is disposed over the substrate and includes a first window conductive region, a first conductive region, a second conductive region, and a third conductive region. The first conductive region is disposed over and is in electrical contact with the first feed terminal; it is also is substantially circular and located within the first window region. The second conductive region is disposed over and is in electrical contact with the second feed terminal; it is also substantially circular and is located within the first window region. The a third conductive region is disposed over and is in electrical contact with the ground terminal, and the third conductive region substantially surrounds the first window region.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Eunyoung Seok, Brian P. Ginsburg, Baher Haroun, Srinath Ramaswamy, Vijay B. Rentala
  • Publication number: 20120306574
    Abstract: A method for providing common-mode feedback is provided. A common-mode current is applied to a common-gate amplifier, and the common-mode current is sensed. In response to the sensed common-mode current, a control voltage is generated. A first feedback current (which is generated in response to the control voltage) can then be applied to differential ground of the common-gate amplifier if the common-mode current is less than a predetermined threshold. Additionally, a second feedback current (which is generated in response to the control voltage) can be applied to input terminals of the common-gate amplifier if the common-mode current is greater than the predetermined threshold.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Brian P. Ginsburg, Vijay B. Rentala, Srinath Ramaswamy, Baher Haroun, Eunyoung Seok
  • Publication number: 20120299797
    Abstract: An apparatus for emitting radiation is provided. The apparatus comprises an antenna formed on a substrate, and a high impedance surface (HIS). The HIS has a plurality of cells formed on the substrate that are arranged to form an array that substantially surrounds at least a portion of the antenna. Each cell generally includes a ground plane, first plate, second plate, and an interconnect. The ground plane is formed on the substrate, while the first plate (which is substantially rectangular) is formed over and coupled to the ground plane. The first plate for each cell is also arranged so as to form a first checkered pattern for the array. The second plate (which is substantially rectangular) is formed over and is substantially parallel to the first plate. The first and second plates are also substantially aligned with a central axis that extends generally perpendicular to the first and second plates hand have a interconnect formed therebetween.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: James N. Murdock, Eunyoung Seok, Brian P. Ginsburg, Vijay B. Rentala, Srinath Ramaswamy, Baher Haroun
  • Publication number: 20120293217
    Abstract: There are a variety of duty cycle systems, such as low noise amplifiers or LNAs, that have a large time varying current consumption, and parasitic inductances and resistance (usually from bondwires in the package) that can significantly affect supply currents. Thus, to compensate for these parasitics, a boost circuit is provided that allows for current to be supplied from a separate supply using a feedforward scheme to perform active decoupling.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Brian P. Ginsburg, Vijay B. Rentala, Srinath Ramaswamy, Baher Haroun, Eunyoung Seok
  • Patent number: 8310308
    Abstract: A method for providing common-mode feedback is provided. A common-mode current is applied to a common-gate amplifier, and the common-mode current is sensed. In response to the sensed common-mode current, a control voltage is generated. A first feedback current (which is generated in response to the control voltage) can then be applied to differential ground of the common-gate amplifier if the common-mode current is less than a predetermined threshold. Additionally, a second feedback current (which is generated in response to the control voltage) can be applied to input terminals of the common-gate amplifier if the common-mode current is greater than the predetermined threshold.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Brian P. Ginsburg, Vijay B. Rentala, Srinath Ramaswamy, Baher Haroun, Eunyoung Seok
  • Patent number: 8125253
    Abstract: A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal and outputs a divided reference signal. The feedback divider portion receives an output signal from the circuit and outputs a divided feedback signal. The phase detector portion outputs a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion outputs a tuning signal based on the phase detector signal. The voltage controlled oscillator portion output the outputs a signal based on the tuning signal. The phase detector portion changes the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: February 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Stanley Goldman, Srinath Ramaswamy
  • Publication number: 20110102030
    Abstract: A circuit is provided for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge. The circuit is operable to receive a reference signal and to output an output signal. The circuit includes an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion is arranged to receive the reference signal and is operable to output a divided reference signal. The feedback divider portion is arranged to receive the output signal and is operable to output a divided feedback signal. The phase detector portion is operable to output a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion is operable to output a tuning signal based on the phase detector signal. The voltage controlled oscillator portion is operable to output the output signal based on the tuning signal.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Inventors: Stanley Goldman, Srinath Ramaswamy
  • Publication number: 20070024366
    Abstract: The summing comparator includes: a first integrator; a second integrator for receiving an output of the first integrator; and a comparator for switching when the output of the first integrator is greater than the output of the second integrator. The outputs of the first and second integrators are directly compared by the comparator without the necessity of a summing amplifier.
    Type: Application
    Filed: March 27, 2006
    Publication date: February 1, 2007
    Inventors: Jagadeesh Krishnan, Srinath Ramaswamy, Gangadhar Burra
  • Publication number: 20070024361
    Abstract: An amplifier system in accordance with an aspect of the present invention comprises a switching amplifier that drives a load with a pulse-width modulated (PWM) output signal that varies between first and second rails based on a first control input signal, and a common mode supply that provides a switching signal that varies between third and fourth rails to maintain a common mode voltage of the load at a level that is between the first and second rails.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 1, 2007
    Inventors: Jagadeesh Krishnan, Srinath Ramaswamy, Gangadhar Burra
  • Publication number: 20070024365
    Abstract: A Class-D amplifier system may include an input stage that includes an Nth order filter, where N>1. The input stage filters an input signal to provide a filtered output signal, an input of the input stage being configured to receive the input signal as a digital pulse-width-modulated (PWM) signal. A comparator provides a quantized output signal based on the filtered output signal. An output stage is connected between a first voltage rail and a second voltage rail. The output stage provides a switching output signal at an output that varies between the first voltage rail and the second voltage rail based on the quantized output signal. A feedback path connects the output of the output stage with the input of the input stage, such that the Nth order filter compensates for variations in at least one of the first voltage rail and the second voltage rail.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 1, 2007
    Inventors: Srinath Ramaswamy, Jagadeesh Krishnan, Gangadhar Burra
  • Publication number: 20060044057
    Abstract: An amplifier having an active and passive gain stage connect to a load for driving a load according to a system analog input. A first embodiment of the amplifier in accordance with the present invention includes a logic network connected between a comparator network and a switching system, wherein the comparator network connects to the passive gain stage. Specifically, the active gain stage may include an active filter connected to receive an analog or digital input and provide a difference between the analog or digital input and the feedback signal relative to the gain factor of a gain unit connected to the active filter. The passive gain stage includes a passive filter. The logic network generates at least one switching signal which controls the switching system that includes at least one switching device to selectively provide power to the load. An output signal from the switching system provides output for the amplifier and is fed back to the active gain stage.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 2, 2006
    Inventors: Rahmi Hezar, Baher Haroun, Brett Forejt, Srinath Ramaswamy