Patents by Inventor Srinivas B. Purushotham
Srinivas B. Purushotham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10831659Abstract: A method handles cache misses using a Scope Resolution Tag Buffer (SRTB). A cache controller assigns each data block in L2 cache with an n-bit value, where the n-bit value describes a quantity of occurrences in which the data block has been accessed, and where the cache controller increments the n-bit value in one or more data blocks in the first level memory cache each time the one or more data blocks are accessed. The cache controller evicts a particular data block from the L2 cache, and stores a particular data block address where the particular data block is now stored in a Scope Resolution Tag Buffer (SRTB). The information in the SRTB is used to locate which cache or memory contains the particular data block in the event of a subsequent cache miss in the L2 cache.Type: GrantFiled: September 28, 2018Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Srinivas B. Purushotham, Naveen Miriyalu, Venkata K. Tavva
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Publication number: 20200104258Abstract: A method handles cache misses using a Scope Resolution Tag Buffer (SRTB). A cache controller assigns each data block in L2 cache with an n-bit value, where the n-bit value describes a quantity of occurrences in which the data block has been accessed, and where the cache controller increments the n-bit value in one or more data blocks in the first level memory cache each time the one or more data blocks are accessed. The cache controller evicts a particular data block from the L2 cache, and stores a particular data block address where the particular data block is now stored in a Scope Resolution Tag Buffer (SRTB). The information in the SRTB is used to locate which cache or memory contains the particular data block in the event of a subsequent cache miss in the L2 cache.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: SRINIVAS B. PURUSHOTHAM, NAVEEN MIRIYALU, VENKATA K. TAVVA
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Patent number: 10078447Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.Type: GrantFiled: November 5, 2015Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham
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Patent number: 10067672Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.Type: GrantFiled: August 31, 2015Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham
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Publication number: 20170060476Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham
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Publication number: 20170060423Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.Type: ApplicationFiled: November 5, 2015Publication date: March 2, 2017Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham
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Patent number: 9515663Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.Type: GrantFiled: June 14, 2016Date of Patent: December 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani
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Publication number: 20160294396Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.Type: ApplicationFiled: June 14, 2016Publication date: October 6, 2016Inventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani
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Patent number: 9419625Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.Type: GrantFiled: August 29, 2014Date of Patent: August 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani
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Publication number: 20160065219Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani