Patents by Inventor Srinivas Beeravolu

Srinivas Beeravolu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Block design containers for circuit design
    Patent number: 11886789
    Abstract: Circuit design development using block design containers can include opening, within a development environment generated by an Electronic Design Automation (EDA) system, a top-level block design specifying a circuit design and inserting, within the top-level block design using the EDA system, a block design container. The block design container specifies a source block design used as a sub-design within the top-level block design.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: January 30, 2024
    Assignee: Xilinx, Inc.
    Inventors: Ayush Khemka, Srinivas Beeravolu, Kalyani Tummala, Jaipal Reddy Nareddy, Adithya Balaji Boda, Suman Kumar Timmireddy
  • Preparation of circuit designs for system-on-chip devices and implementation of circuitry using instances of a logical network-on-chip
    Patent number: 10977401
    Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Jeffrey M. Arnold, Stephen L. Bade, Srinivas Beeravolu, Chukwuweta Chukwudebe, Anindita Patra, Nabeel Shirazi
  • Hardware-software design flow for heterogeneous and programmable devices
    Patent number: 10891414
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele
  • HARDWARE-SOFTWARE DESIGN FLOW FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
    Publication number: 20200372123
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele
  • System level circuit design
    Patent number: 8769449
    Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Adam P. Donlin, Biping Wu, Kyle Corbett, Nabeel Shirazi, Shay P. Seng, Amit Kasat, Srinivas Beeravolu, Khang K. Dao, Jeffrey H. Seltzer, Christopher J. Case