Patents by Inventor Srinivas Chennupaty

Srinivas Chennupaty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119129
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Performing AES encryption or decryption in multiple modes with a single instruction
    Patent number: 9325498
    Abstract: A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Martin Dixon, Srinivas Chennupaty, Shay Gueron
  • Instruction and logic for processing text strings
    Patent number: 9069547
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150178079
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 25, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150178082
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 25, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150178083
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 25, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150178084
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 25, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150178081
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 25, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150178080
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 25, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • Instruction and logic for processing text strings
    Patent number: 9063720
    Abstract: Instruction, method, apparatus, and processing systems for performing a string comparison operation. An apparatus includes execution resources to execute a single-instruction-multiple-data (SIMD) comparison instruction. In response to the SIMD comparison instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150169474
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 18, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150169473
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 18, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150154122
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 4, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150106594
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150104007
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 16, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150106592
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150106593
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS
    Publication number: 20150106591
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150104009
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 16, 2015
    Applicant: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150104010
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 16, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis