Abstract: Methods and apparatus to create software basic block layouts are disclosed. In one example, a method identifies branch data associated with a plurality of machine accessible instructions and identifies a plurality of basic blocks associated with the branch data. The method generates a partial layout from the plurality of basic blocks and generates a substantial layout from the partial layout based on a cost metric.

Abstract: A method including analyzing a program to obtain information about variables within the program, generating a call graph based on the information, determining all possible aliases for each variable, identifying parallel accesses by two variables, a variable and an alias, and/or two aliases during an instruction in the program, generating an interference graph based on the parallel accesses, and assigning the variables to logical stacks based on the interference graph.

Abstract: A method for setting a breakpoint includes the following: receiving an input specifying a location for insertion of a breakpoint in the executable program; determining a breakpoint address for insertion of the breakpoint in the executable program based on the specified location of the breakpoint; writing a breakpoint instruction into a second machine-accessible medium at the breakpoint address; and locking a line containing the breakpoint instruction into the second machine-accessible medium to prevent the breakpoint instruction from being overwritten.

Abstract: Methods and apparatus to create software basic block layouts are disclosed. In one example, a method identifies branch data associated with a plurality of machine accessible instructions and identifies a plurality of basic blocks associated with the branch data. The method generates a partial layout from the plurality of basic blocks and generates a substantial layout from the partial layout based on a cost metric.

Abstract: A method including analyzing a program to obtain information about variables within the program, generating a call graph based on the information, determining all possible aliases for each variable, identifying parallel accesses by two variables, a variable and an alias, and/or two aliases during an instruction in the program, generating an interference graph based on the parallel accesses, and assigning the variables to logical stacks based on the interference graph.

Abstract: In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.