Patents by Inventor Srinivas Doddi

Srinivas Doddi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8677301
    Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 18, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ya-Chieh Lai, Frank Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
  • Patent number: 8645887
    Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: February 4, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
  • Patent number: 8381152
    Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: February 19, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
  • Patent number: 8302052
    Abstract: Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: October 30, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Brian Lee, Srinivas Doddi, Ron Pyke, Taber Smith, Emmanuel Drege
  • Publication number: 20120272201
    Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 25, 2012
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ya-Chieh Lai, Frank Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
  • Publication number: 20120272200
    Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 25, 2012
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
  • Publication number: 20100324878
    Abstract: Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 23, 2010
    Applicant: Cadence Design Systems, Inc.
    Inventors: Brian LEE, Srinivas DODDI, Ron PYKE, Taber SMITH, Emmanuel DREGE
  • Patent number: 7831528
    Abstract: A structure formed on a semiconductor wafer is examined by obtaining a first diffraction signal measured using a metrology device. A second diffraction signal is generated using a machine learning system, where the machine learning system receives as an input one or more parameters that characterize a profile of the structure to generate the second diffraction signal. The first and second diffraction signals are compared. When the first and second diffraction signals match within a matching criterion, a feature of the structure is determined based on the one or more parameters or the profile used by the machine learning system to generate the second diffraction signal.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: November 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Srinivas Doddi, Emmanuel Drege, Nickhil Jakatdar, Junwei Bao
  • Publication number: 20090307642
    Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 10, 2009
    Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
  • Publication number: 20090198635
    Abstract: A structure formed on a semiconductor wafer is examined by obtaining a first diffraction signal measured using a metrology device. A second diffraction signal is generated using a machine learning system, where the machine learning system receives as an input one or more parameters that characterize a profile of the structure to generate the second diffraction signal. The first and second diffraction signals are compared. When the first and second diffraction signals match within a matching criterion, a feature of the structure is determined based on the one or more parameters or the profile used by the machine learning system to generate the second diffraction signal.
    Type: Application
    Filed: March 5, 2009
    Publication date: August 6, 2009
    Applicant: Timbre Technologies, Inc.
    Inventors: Srinivas Doddi, Emmanuel Drege, Nickhil Jakatdar, Junwei Bao
  • Patent number: 7523076
    Abstract: A profile model can be selected for use in examining a structure formed on a semiconductor wafer using optical metrology by obtaining an initial profile model having a set of profile parameters. A machine learning system is trained using the initial profile model. A simulated diffraction signal is generated for an optimized profile model using the trained machine learning system, where the optimized profile model has a set of profile parameters with the same or fewer profile parameters than the initial profile model. A determination is made as to whether the one or more termination criteria are met. If the one or more termination criteria are met, the optimized profile model is modified and another simulated diffraction signal is generated using the same trained machine learning system.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: April 21, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Emmanuel Drege, Srinivas Doddi, Junwei Bao
  • Patent number: 7505153
    Abstract: A profile model for use in optical metrology of structures in a wafer is selected, the profile model having a set of geometric parameters associated with the dimensions of the structure. The set of geometric parameters is selected to a set of optimization parameters. The number of optimization parameters within the set of optimization parameters is less than the number of geometric parameters within the set of geometric parameters. A set of selected optimization parameters is selected from the set of optimization parameters. The parameters of the set of selected geometric parameters are used as parameters of the selected profile model. The selected profile model is tested against one or more termination criteria.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: March 17, 2009
    Assignee: Timbre Technologies, Inc.
    Inventors: Vi Vuong, Emmanuel Drege, Junwei Bao, Srinivas Doddi, Xinhui Niu, Nickhil Jakatdar
  • Patent number: 7474993
    Abstract: Specific wavelengths to use in optical metrology of an integrated circuit can be selected using one or more selection criteria and termination criteria. Wavelengths are selected using the selection criteria, and the selection of wavelengths is iterated until the termination criteria are met.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: January 6, 2009
    Assignee: Timbre Technologies, Inc.
    Inventors: Srinivas Doddi, Lawrence Lane, Vi Vuong, Michael Laughery, Junwei Bao, Kelly Barry, Nickhil Jakatdar, Emmanuel Drege
  • Patent number: 7428060
    Abstract: The number of diffraction orders to use in generating simulated diffraction signals for a two-dimensional structure in optical metrology is selected by generating a first simulated diffraction signal using a first number of diffraction orders and a hypothetical profile of the two-dimensional structure. A second simulated diffraction signal is generated using a second number of diffraction orders using the same hypothetical profile used to generate the first simulated diffraction signal, where the first and second numbers of diffraction orders are different. The first and second simulated diffraction signals are compared. Based on the comparison of the first and second simulated diffraction signals, a determination is made as to whether to select the first or second number of diffraction orders.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: September 23, 2008
    Assignee: Timbre Technologies, Inc.
    Inventors: Wen Jin, Srinivas Doddi, Shifang Li
  • Patent number: 7394554
    Abstract: A hypothetical profile is used to model the profile of a structure formed on a semiconductor wafer to use in determining the profile of the structure using optical metrology. To select a hypothetical profile, sample diffraction signals are obtained from measured diffraction signals of structures formed on the wafer, where the sample diffraction signals are a representative sampling of the measured diffraction signals. A hypothetical profile is defined and evaluated using a sample diffraction signal from the obtained sample diffraction signals.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: July 1, 2008
    Assignee: Timbre Technologies, Inc.
    Inventors: Vi Vuong, Junwei Bao, Srinivas Doddi, Emmanuel Drege, Jin Wen, Sanjay Yedur, Doris Chin, Nickhil Jakatdar, Lawrence Lane
  • Publication number: 20080151269
    Abstract: A profile model for use in optical metrology of structures in a wafer is selected, the profile model having a set of geometric parameters associated with the dimensions of the structure. The set of geometric parameters is selected to a set of optimization parameters. The number of optimization parameters within the set of optimization parameters is less than the number of geometric parameters within the set of geometric parameters. A set of selected optimization parameters is selected from the set of optimization parameters. The parameters of the set of selected geometric parameters are used as parameters of the selected profile model. The selected profile model is tested against one or more termination criteria.
    Type: Application
    Filed: February 12, 2008
    Publication date: June 26, 2008
    Applicant: Timbre Technologies, Inc.
    Inventors: Vi Vuong, Emmanuel Drege, Junwei Bao, Srinivas Doddi, Xinhui Niu, Nickhil Jakatdar
  • Patent number: 7330279
    Abstract: A profile model for use in optical metrology of structures in a wafer is selected, the profile model having a set of geometric parameters associated with the dimensions of the structure. A set of optimization parameters is selected for the profile model using one or more input diffraction signals and one or more parameter selection criteria. The selected profile model and the set of optimization parameters are tested against one or more termination criteria. The process of selecting a profile model, selecting a set of optimization parameters, and testing the selected profile model and set of optimization parameters is performed until the one or more termination criteria are met.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: February 12, 2008
    Assignee: Timbre Technologies, Inc.
    Inventors: Vi Vuong, Emmanuel Drege, Junwei Bao, Srinivas Doddi, Xinhui Niu, Nickhil Jakatdar
  • Publication number: 20070223011
    Abstract: The number of diffraction orders to use in generating simulated diffraction signals for a two-dimensional structure in optical metrology is selected by generating a first simulated diffraction signal using a first number of diffraction orders and a hypothetical profile of the two-dimensional structure. A second simulated diffraction signal is generated using a second number of diffraction orders using the same hypothetical profile used to generate the first simulated diffraction signal, where the first and second numbers of diffraction orders are different. The first and second simulated diffraction signals are compared. Based on the comparison of the first and second simulated diffraction signals, a determination is made as to whether to select the first or second number of diffraction orders.
    Type: Application
    Filed: March 24, 2006
    Publication date: September 27, 2007
    Applicant: Timbre Technologies, Inc.
    Inventors: Wen Jin, Srinivas Doddi, Shifang Li
  • Publication number: 20070198211
    Abstract: Specific wavelengths to use in optical metrology of an integrated circuit can be selected using one or more selection criteria and termination criteria. Wavelengths are selected using the selection criteria, and the selection of wavelengths is iterated until the termination criteria are met.
    Type: Application
    Filed: April 20, 2007
    Publication date: August 23, 2007
    Applicant: Timbre Technologies, Inc.
    Inventors: Srinivas Doddi, Lawrence Lane, Vi Vuong, Michael Laughery, Junwei Bao, Kelly Barry, Nickhil Jakatdar, Emmanuel Drege
  • Patent number: 7216045
    Abstract: Specific wavelengths to use in optical metrology of an integrated circuit can be selected using one or more selection criteria and termination criteria. Wavelengths are selected using the selection criteria, and the selection of wavelengths is iterated until the termination criteria are met.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: May 8, 2007
    Assignee: Timbre Technologies, Inc.
    Inventors: Srinivas Doddi, Lawrence Lane, Vi Vuong, Mike Laughery, Junwei Bao, Kelly Barry, Nickhil Jakatdar, Emmanuel Drege