Patents by Inventor Srinivas Doddi
Srinivas Doddi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8677301Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: GrantFiled: June 27, 2012Date of Patent: March 18, 2014Assignee: Cadence Design Systems, Inc.Inventors: Ya-Chieh Lai, Frank Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Patent number: 8645887Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: GrantFiled: June 27, 2012Date of Patent: February 4, 2014Assignee: Cadence Design Systems, Inc.Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Patent number: 8381152Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: GrantFiled: June 5, 2008Date of Patent: February 19, 2013Assignee: Cadence Design Systems, Inc.Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Patent number: 8302052Abstract: Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.Type: GrantFiled: June 23, 2009Date of Patent: October 30, 2012Assignee: Cadence Design Systems, Inc.Inventors: Brian Lee, Srinivas Doddi, Ron Pyke, Taber Smith, Emmanuel Drege
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Publication number: 20120272201Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Ya-Chieh Lai, Frank Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Publication number: 20120272200Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Publication number: 20100324878Abstract: Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.Type: ApplicationFiled: June 23, 2009Publication date: December 23, 2010Applicant: Cadence Design Systems, Inc.Inventors: Brian LEE, Srinivas DODDI, Ron PYKE, Taber SMITH, Emmanuel DREGE
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Patent number: 7831528Abstract: A structure formed on a semiconductor wafer is examined by obtaining a first diffraction signal measured using a metrology device. A second diffraction signal is generated using a machine learning system, where the machine learning system receives as an input one or more parameters that characterize a profile of the structure to generate the second diffraction signal. The first and second diffraction signals are compared. When the first and second diffraction signals match within a matching criterion, a feature of the structure is determined based on the one or more parameters or the profile used by the machine learning system to generate the second diffraction signal.Type: GrantFiled: March 5, 2009Date of Patent: November 9, 2010Assignee: Tokyo Electron LimitedInventors: Srinivas Doddi, Emmanuel Drege, Nickhil Jakatdar, Junwei Bao
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Publication number: 20090307642Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: ApplicationFiled: June 5, 2008Publication date: December 10, 2009Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Publication number: 20090198635Abstract: A structure formed on a semiconductor wafer is examined by obtaining a first diffraction signal measured using a metrology device. A second diffraction signal is generated using a machine learning system, where the machine learning system receives as an input one or more parameters that characterize a profile of the structure to generate the second diffraction signal. The first and second diffraction signals are compared. When the first and second diffraction signals match within a matching criterion, a feature of the structure is determined based on the one or more parameters or the profile used by the machine learning system to generate the second diffraction signal.Type: ApplicationFiled: March 5, 2009Publication date: August 6, 2009Applicant: Timbre Technologies, Inc.Inventors: Srinivas Doddi, Emmanuel Drege, Nickhil Jakatdar, Junwei Bao
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Patent number: 7523076Abstract: A profile model can be selected for use in examining a structure formed on a semiconductor wafer using optical metrology by obtaining an initial profile model having a set of profile parameters. A machine learning system is trained using the initial profile model. A simulated diffraction signal is generated for an optimized profile model using the trained machine learning system, where the optimized profile model has a set of profile parameters with the same or fewer profile parameters than the initial profile model. A determination is made as to whether the one or more termination criteria are met. If the one or more termination criteria are met, the optimized profile model is modified and another simulated diffraction signal is generated using the same trained machine learning system.Type: GrantFiled: March 1, 2004Date of Patent: April 21, 2009Assignee: Tokyo Electron LimitedInventors: Emmanuel Drege, Srinivas Doddi, Junwei Bao
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Patent number: 7505153Abstract: A profile model for use in optical metrology of structures in a wafer is selected, the profile model having a set of geometric parameters associated with the dimensions of the structure. The set of geometric parameters is selected to a set of optimization parameters. The number of optimization parameters within the set of optimization parameters is less than the number of geometric parameters within the set of geometric parameters. A set of selected optimization parameters is selected from the set of optimization parameters. The parameters of the set of selected geometric parameters are used as parameters of the selected profile model. The selected profile model is tested against one or more termination criteria.Type: GrantFiled: February 12, 2008Date of Patent: March 17, 2009Assignee: Timbre Technologies, Inc.Inventors: Vi Vuong, Emmanuel Drege, Junwei Bao, Srinivas Doddi, Xinhui Niu, Nickhil Jakatdar
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Patent number: 7474993Abstract: Specific wavelengths to use in optical metrology of an integrated circuit can be selected using one or more selection criteria and termination criteria. Wavelengths are selected using the selection criteria, and the selection of wavelengths is iterated until the termination criteria are met.Type: GrantFiled: April 20, 2007Date of Patent: January 6, 2009Assignee: Timbre Technologies, Inc.Inventors: Srinivas Doddi, Lawrence Lane, Vi Vuong, Michael Laughery, Junwei Bao, Kelly Barry, Nickhil Jakatdar, Emmanuel Drege
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Patent number: 7428060Abstract: The number of diffraction orders to use in generating simulated diffraction signals for a two-dimensional structure in optical metrology is selected by generating a first simulated diffraction signal using a first number of diffraction orders and a hypothetical profile of the two-dimensional structure. A second simulated diffraction signal is generated using a second number of diffraction orders using the same hypothetical profile used to generate the first simulated diffraction signal, where the first and second numbers of diffraction orders are different. The first and second simulated diffraction signals are compared. Based on the comparison of the first and second simulated diffraction signals, a determination is made as to whether to select the first or second number of diffraction orders.Type: GrantFiled: March 24, 2006Date of Patent: September 23, 2008Assignee: Timbre Technologies, Inc.Inventors: Wen Jin, Srinivas Doddi, Shifang Li
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Patent number: 7394554Abstract: A hypothetical profile is used to model the profile of a structure formed on a semiconductor wafer to use in determining the profile of the structure using optical metrology. To select a hypothetical profile, sample diffraction signals are obtained from measured diffraction signals of structures formed on the wafer, where the sample diffraction signals are a representative sampling of the measured diffraction signals. A hypothetical profile is defined and evaluated using a sample diffraction signal from the obtained sample diffraction signals.Type: GrantFiled: September 15, 2003Date of Patent: July 1, 2008Assignee: Timbre Technologies, Inc.Inventors: Vi Vuong, Junwei Bao, Srinivas Doddi, Emmanuel Drege, Jin Wen, Sanjay Yedur, Doris Chin, Nickhil Jakatdar, Lawrence Lane
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Publication number: 20080151269Abstract: A profile model for use in optical metrology of structures in a wafer is selected, the profile model having a set of geometric parameters associated with the dimensions of the structure. The set of geometric parameters is selected to a set of optimization parameters. The number of optimization parameters within the set of optimization parameters is less than the number of geometric parameters within the set of geometric parameters. A set of selected optimization parameters is selected from the set of optimization parameters. The parameters of the set of selected geometric parameters are used as parameters of the selected profile model. The selected profile model is tested against one or more termination criteria.Type: ApplicationFiled: February 12, 2008Publication date: June 26, 2008Applicant: Timbre Technologies, Inc.Inventors: Vi Vuong, Emmanuel Drege, Junwei Bao, Srinivas Doddi, Xinhui Niu, Nickhil Jakatdar
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Patent number: 7330279Abstract: A profile model for use in optical metrology of structures in a wafer is selected, the profile model having a set of geometric parameters associated with the dimensions of the structure. A set of optimization parameters is selected for the profile model using one or more input diffraction signals and one or more parameter selection criteria. The selected profile model and the set of optimization parameters are tested against one or more termination criteria. The process of selecting a profile model, selecting a set of optimization parameters, and testing the selected profile model and set of optimization parameters is performed until the one or more termination criteria are met.Type: GrantFiled: July 25, 2002Date of Patent: February 12, 2008Assignee: Timbre Technologies, Inc.Inventors: Vi Vuong, Emmanuel Drege, Junwei Bao, Srinivas Doddi, Xinhui Niu, Nickhil Jakatdar
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Publication number: 20070223011Abstract: The number of diffraction orders to use in generating simulated diffraction signals for a two-dimensional structure in optical metrology is selected by generating a first simulated diffraction signal using a first number of diffraction orders and a hypothetical profile of the two-dimensional structure. A second simulated diffraction signal is generated using a second number of diffraction orders using the same hypothetical profile used to generate the first simulated diffraction signal, where the first and second numbers of diffraction orders are different. The first and second simulated diffraction signals are compared. Based on the comparison of the first and second simulated diffraction signals, a determination is made as to whether to select the first or second number of diffraction orders.Type: ApplicationFiled: March 24, 2006Publication date: September 27, 2007Applicant: Timbre Technologies, Inc.Inventors: Wen Jin, Srinivas Doddi, Shifang Li
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Publication number: 20070198211Abstract: Specific wavelengths to use in optical metrology of an integrated circuit can be selected using one or more selection criteria and termination criteria. Wavelengths are selected using the selection criteria, and the selection of wavelengths is iterated until the termination criteria are met.Type: ApplicationFiled: April 20, 2007Publication date: August 23, 2007Applicant: Timbre Technologies, Inc.Inventors: Srinivas Doddi, Lawrence Lane, Vi Vuong, Michael Laughery, Junwei Bao, Kelly Barry, Nickhil Jakatdar, Emmanuel Drege
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Patent number: 7216045Abstract: Specific wavelengths to use in optical metrology of an integrated circuit can be selected using one or more selection criteria and termination criteria. Wavelengths are selected using the selection criteria, and the selection of wavelengths is iterated until the termination criteria are met.Type: GrantFiled: June 3, 2002Date of Patent: May 8, 2007Assignee: Timbre Technologies, Inc.Inventors: Srinivas Doddi, Lawrence Lane, Vi Vuong, Mike Laughery, Junwei Bao, Kelly Barry, Nickhil Jakatdar, Emmanuel Drege